One clock is enough

[clump.git] / eval.v

diff --git a/eval.v b/eval.v
index 8aa21590ca0ea88af0f0667a3b4db5b14f1dcddc..75a979c6a89691932a23d36f1dbda0d99adb27bf 100644 (file)
--- a/eval.v
+++ b/eval.v
@@ -1,11 +1,13 @@
-module EVAL(input clk, input mclk, input [15:0] Ein, output [15:0] Eout, output [3:0] gcop, output [5:0] ostate, input conn_ea, input conn_et);
+module EVAL(input clk, input clk_enable, input [15:0] Ein, output [15:0] Eout, output [3:0] gcop, output [5:0] ostate, input conn_ea, input conn_et);
    reg [21:0] rom_output;
    reg [5:0]  eostate = 6'o0;
    reg [5:0]  enstate;
    reg [15:0]  Ein_latched;
 
    always @(posedge clk) begin
-         Ein_latched <= Ein;
+         if(clk_enable) begin
+                Ein_latched <= Ein;
+         end
    end
 
    wire et_lit = rom_output[21];
@@ -94,10 +96,12 @@ module EVAL(input clk, input mclk, input [15:0] Ein, output [15:0] Eout, output
    end // always @ *
 
    always @ (posedge clk) begin
-         eostate <=
-                               et_disp ? (enstate | E[15:13]) :
-                               eaz_etz_eqv_disp ? (enstate | {ea_zero, et_zero, 1'b0}) :
-                               enstate;
+         if (clk_enable) begin
+                eostate <=
+                                  et_disp ? (enstate | E[15:13]) :
+                                  eaz_etz_eqv_disp ? (enstate | {ea_zero, et_zero, 1'b0}) :
+                                  enstate;
+         end
    end
 
    assign ostate = eostate;
@@ -127,10 +131,12 @@ module EVAL(input clk, input mclk, input [15:0] Ein, output [15:0] Eout, output
    assign Eout = EfromV | EfromX | EfromXp | EfromN | EfromL | EfromC | EfromLIT;
 
    always @ (posedge clk) begin
-         if (ldV) V <= E;
-         if (ldX) X <= E;
-         if (ldN) N <= E;
-         if (ldL) L <= E;
-         if (ldC) C <= E;
+         if (clk_enable) begin
+                if (ldV) V <= E;
+                if (ldX) X <= E;
+                if (ldN) N <= E;
+                if (ldL) L <= E;
+                if (ldC) C <= E;
+         end
    end
 endmodule // EVAL