reg [21:0] rom_output;
reg [5:0] eostate;
reg [5:0] enstate;
- reg [15:0] Ein_latched;
- always @(posedge clk) begin
- if(clk_enable) begin
- Ein_latched <= Ein;
- end
- end
+`ifdef SIM
+ initial eostate <= 0;
+`endif
wire et_lit = rom_output[21];
wire ea_lit = rom_output[20];