`include "gcram.v"
-module GC (input clk, input mclk, input [15:0] Ein, output [15:0] Eout, input [3:0] gcop, output [5:0] ostate, output conn_et, output conn_ea, output step_eval, output ram_we, output [12:0] ram_addr, output [15:0] ram_di, input [15:0] ram_do);
+module GC (input clk, input clk_enable, input [15:0] Ein, output [15:0] Eout, input [3:0] gcop, output [5:0] ostate, output conn_et, output conn_ea, output step_eval, output ram_we, output [12:0] ram_addr, output [15:0] ram_di, input [15:0] ram_do);
reg [15:0] rom_output;
reg [5:0] gostate = 6'o0;
reg [5:0] gnstate;
reg [15:0] Ein_latched = 16'b0100000000000100; // initial value of E
always @(posedge clk) begin
- Ein_latched <= Ein;
+ if(clk_enable) begin
+ Ein_latched <= Ein;
+ end
end
wire ga_zero_disp = rom_output[15];
end // always @ *
always @ (posedge clk) begin
- gostate <=
- ga_zero_disp ? (gnstate | ga_zero) :
- gcop_disp ? (gnstate | gcop) :
- gnstate;
+ if(clk_enable) begin
+ gostate <=
+ ga_zero_disp ? (gnstate | ga_zero) :
+ gcop_disp ? (gnstate | gcop) :
+ gnstate;
+ end
end // always @ (posedge clk)
assign ostate = gostate;
assign Eout[15:13] = conn_et ? Gout[15:13] : 0;
always @ (posedge clk) begin
- if (ldS) S = G;
- if (ldP) P <= G[12:0];
- if (ldR) R <= G;
- if (ldQ) Q <= G;
- if (adr) A <= S[12:0];
+ if(clk_enable) begin
+ if (ldS) S = G;
+ if (ldP) P <= G[12:0];
+ if (ldR) R <= G;
+ if (ldQ) Q <= G;
+ if (adr) A <= S[12:0];
+ end
end
endmodule // GC