module GC (input clk, input mclk, input [7:0] Ein, output [7:0] Eout, input [3:0] gcop, output [5:0] ostate, output step_eval);
reg [5:0] gostate = 6'o2;
reg [5:0] gnstate;
- reg [16:0] rom_output;
+ reg [15:0] rom_output;
reg [7:0] Ein_latched;
always @(posedge clk) begin