Make words 16 bits wide

[clump.git] / gc.v

diff --git a/gc.v b/gc.v
index 682f51a89134bde756dcd3ec1cf1d50d643c903e..ceae7d7a23ada8d40115ec03879aee6dbd69fff6 100644 (file)
--- a/gc.v
+++ b/gc.v
@@ -1,10 +1,10 @@
 `include "gcram.v"
 
-module GC (input clk, input mclk, input [7:0] Ein, output [7:0] Eout, input [3:0] gcop, output [5:0] ostate, output conn_et, output conn_ea, output step_eval, output [7:0] result);
+module GC (input clk, input mclk, input [15:0] Ein, output [15:0] Eout, input [3:0] gcop, output [5:0] ostate, output conn_et, output conn_ea, output step_eval, output [15:0] result);
    reg [15:0] rom_output;
    reg [5:0]  gostate = 6'o0;
    reg [5:0]  gnstate;
-   reg [7:0]  Ein_latched = 6'h44; // initial value of E
+   reg [15:0] Ein_latched = 16'b0100000000000100; // initial value of E
 
    always @(posedge clk) begin
          Ein_latched <= Ein;
@@ -27,7 +27,7 @@ module GC (input clk, input mclk, input [7:0] Ein, output [7:0] Eout, input [3:0
    assign conn_ea    = rom_output[1];
    assign step_eval  = rom_output[0];
 
-   wire ga_zero = ~|G[7:5];
+   wire ga_zero = ~|G[12:0];
 
    always @* begin
          case(gostate)
@@ -36,7 +36,7 @@ module GC (input clk, input mclk, input [7:0] Ein, output [7:0] Eout, input [3:0
                6'o02:   begin rom_output <= 16'o040000; gnstate <= 6'o20; end
                6'o03:   begin rom_output <= 16'o000126; gnstate <= 6'o04; end
                6'o04:   begin rom_output <= 16'o001200; gnstate <= 6'o05; end
-               6'o05:   begin rom_output <= 16'o002020; gnstate <= 6'o06; end
+               6'o05:   begin rom_output <= 16'o002020 | (1 << 12); gnstate <= 6'o06; end
                6'o06:   begin rom_output <= 16'o000051; gnstate <= 6'o02; end
                6'o07:   begin rom_output <= 16'o002020; gnstate <= 6'o10; end
                6'o10:   begin rom_output <= 16'o001200; gnstate <= 6'o11; end
@@ -92,53 +92,40 @@ module GC (input clk, input mclk, input [7:0] Ein, output [7:0] Eout, input [3:0
 
    assign ostate = gostate;
 
-   reg [4:0] P;
-   reg [7:0] Q;
-   reg [7:0] R;
-   reg [7:0] S;
+   reg [12:0] P;
+   reg [15:0] Q;
+   reg [15:0] R;
+   reg [15:0] S;
 
-   reg [4:0] A; // latched address
+   reg [12:0] A; // latched address
 
-   wire [7:0] I;
+   wire [15:0] I;
 
-   wire [7:0] G;
-   wire [7:0] Gout;
+   wire [15:0] G;
+   wire [15:0] Gout;
 
-   /*
-   assign G = rdR ? R : 8'bzzzzzzzz;
-   assign G = rdQ ? Q : 8'bzzzzzzzz;
-   assign G = rdP ? {3'b0, P} : 8'bzzzzzzzz;
-   assign G = rdP_plus ? {3'b0, P+1} : 8'bzzzzzzzz;
-   assign G = conn_i ? I : 8'bzzzzzzzz;
-   assign G[4:0] = conn_ea ? E[4:0] : 5'bzzzzz;
-   assign G[7:5] = conn_et ? E[7:5] : 3'bzzz;
-
-   assign E[4:0] = conn_ea ? G[4:0] : 5'bzzzzz;
-   assign E[7:5] = conn_et ? G[7:5] : 3'bzzz;
-       */
-
-   wire [7:0] GfromR = rdR ? R : 0;
-   wire [7:0] GfromQ = rdQ ? Q : 0;
-   wire [7:0] GfromP = rdP ? {3'b0, P} : 0;
-   wire [7:0] GfromP_plus = rdP_plus ? {3'b0, P + 1} : 0;
-   wire [7:0] GfromI = conn_i ? I : 0;
-   wire [4:0] GAfromE = conn_ea ? Ein_latched[4:0] : 0;
-   wire [3:0] GTfromE = conn_et ? Ein_latched[7:5] : 0;
-   wire [7:0] GfromE = {GTfromE, GAfromE};
+   wire [15:0] GfromR = rdR ? R : 0;
+   wire [15:0] GfromQ = rdQ ? Q : 0;
+   wire [15:0] GfromP = rdP ? {3'b0, P} : 0;
+   wire [15:0] GfromP_plus = rdP_plus ? {3'b0, P + 1} : 0;
+   wire [15:0] GfromI = conn_i ? I : 0;
+   wire [12:0] GAfromE = conn_ea ? Ein_latched[12:0] : 0;
+   wire [2:0] GTfromE = conn_et ? Ein_latched[15:13] : 0;
+   wire [15:0] GfromE = {GTfromE, GAfromE};
 
    assign G = GfromR | GfromQ | GfromP | GfromP_plus | GfromI | GfromE;
    assign Gout = GfromR | GfromQ | GfromP | GfromP_plus | GfromI;
 
-   assign Eout[4:0] = conn_ea ? Gout[4:0] : 0;
-   assign Eout[7:5] = conn_et ? Gout[7:5] : 0;
+   assign Eout[12:0]  = conn_ea ? Gout[12:0]  : 0;
+   assign Eout[15:13] = conn_et ? Gout[15:13] : 0;
 
    GCRAM gcram (.clk(mclk), .we(write), .addr(A), .do(I), .di(S), .result(result));
 
    always @ (posedge clk) begin
          if (ldS) S = G;
-         if (ldP) P <= G[4:0];
+         if (ldP) P <= G[12:0];
          if (ldR) R <= G;
          if (ldQ) Q <= G;
-         if (adr) A <= S[4:0];
+         if (adr) A <= S[12:0];
    end
 endmodule // GC