Add diagrams and pictures

[clump.git] / gc.v

diff --git a/gc.v b/gc.v
index 2bbada4f0aeac15103c0643e91274aa3feb550d9..d0da0c1b3beb3c7b31327a9009566c4a4e9bf50e 100644 (file)
--- a/gc.v
+++ b/gc.v
@@ -1,16 +1,15 @@
 `include "gcram.v"
 
-module GC (input clk, input clk_enable, input [15:0] Ein, output [15:0] Eout, input [3:0] gcop, output [5:0] ostate, output conn_et, output conn_ea, output step_eval, output ram_we, output [12:0] ram_addr, output [15:0] ram_di, input [15:0] ram_do);
+module GC (input clk, input clk_enable, input [15:0] Ein, output [15:0] Eout, input [3:0] gcop, output [5:0] ostate, output conn_et, output conn_ea, output step_eval, output ram_we, output [12:0] ram_addr, output [15:0] ram_di, input [15:0] ram_do, output [12:0] freeptr);
    reg [15:0] rom_output;
-   reg [5:0]  gostate = 6'o0;
+   reg [5:0]  gostate;
    reg [5:0]  gnstate;
-   reg [15:0] Ein_latched = 16'b0100000000000100; // initial value of E
 
-   always @(posedge clk) begin
-         if(clk_enable) begin
-               Ein_latched <= Ein;
-         end
+`ifdef SIM
+   initial begin
+         gostate <= 0;
    end
+`endif
 
    wire ga_zero_disp = rom_output[15];
    wire gcop_disp    = rom_output[14];
@@ -86,12 +85,13 @@ module GC (input clk, input clk_enable, input [15:0] Ein, output [15:0] Eout, in
    end // always @ *
 
    always @ (posedge clk) begin
-         if(clk_enable) begin
-                gostate <=
-                                  ga_zero_disp ? (gnstate | ga_zero) :
-                                  gcop_disp ? (gnstate | gcop) :
-                                  gnstate;
-         end
+         if(clk_enable)
+               gostate <=
+                                 ga_zero_disp ? (gnstate | ga_zero) :
+                                 gcop_disp ? (gnstate | gcop) :
+                                 gnstate;
+         else
+               gostate <= 0;
    end // always @ (posedge clk)
 
    assign ostate = gostate;
@@ -103,6 +103,7 @@ module GC (input clk, input clk_enable, input [15:0] Ein, output [15:0] Eout, in
 
    reg [12:0] A; // latched address
 
+   assign freeptr = P;
    assign ram_addr = A;
    assign ram_di = S;
 
@@ -114,8 +115,8 @@ module GC (input clk, input clk_enable, input [15:0] Ein, output [15:0] Eout, in
    wire [15:0] GfromP = rdP ? {3'b0, P} : 0;
    wire [15:0] GfromP_plus = rdP_plus ? {3'b0, P + 1} : 0;
    wire [15:0] GfromI = conn_i ? ram_do : 0;
-   wire [12:0] GAfromE = conn_ea ? Ein_latched[12:0] : 0;
-   wire [2:0] GTfromE = conn_et ? Ein_latched[15:13] : 0;
+   wire [12:0] GAfromE = conn_ea ? Ein[12:0] : 0;
+   wire [2:0] GTfromE = conn_et ? Ein[15:13] : 0;
    wire [15:0] GfromE = {GTfromE, GAfromE};
 
    assign G = GfromR | GfromQ | GfromP | GfromP_plus | GfromI | GfromE;