-module GC (input clk, input mclk, input [7:0] Ein, output [7:0] Eout, input [3:0] gcop, output [5:0] ostate, output step_eval);
- reg [5:0] gostate = 6'o2;
- reg [5:0] gnstate;
+`include "gcram.v"
+
+module GC (input clk, input clk_enable, input [15:0] Ein, output [15:0] Eout, input [3:0] gcop, output [5:0] ostate, output conn_et, output conn_ea, output step_eval, output ram_we, output [12:0] ram_addr, output [15:0] ram_di, input [15:0] ram_do, output [12:0] freeptr);
reg [15:0] rom_output;
- reg [7:0] Ein_latched;
+ reg [5:0] gostate;
+ reg [5:0] gnstate;
- always @(posedge clk) begin
- Ein_latched <= Ein;
+`ifdef SIM
+ initial begin
+ gostate <= 0;
end
+`endif
wire ga_zero_disp = rom_output[15];
wire gcop_disp = rom_output[14];
- wire write = rom_output[13];
+ assign ram_we = rom_output[13];
wire adr = rom_output[12];
wire rdR = rom_output[11];
wire rdQ = rom_output[10];
wire ldQ = rom_output[5];
wire ldP = rom_output[4];
wire conn_i = rom_output[3];
- wire conn_et = rom_output[2];
- wire conn_ea = rom_output[1];
+ assign conn_et = rom_output[2];
+ assign conn_ea = rom_output[1];
assign step_eval = rom_output[0];
- wire ga_zero = ~|G[7:5];
+ wire ga_zero = ~|G[12:0];
always @* begin
case(gostate)
6'o02: begin rom_output <= 16'o040000; gnstate <= 6'o20; end
6'o03: begin rom_output <= 16'o000126; gnstate <= 6'o04; end
6'o04: begin rom_output <= 16'o001200; gnstate <= 6'o05; end
- 6'o05: begin rom_output <= 16'o002020; gnstate <= 6'o06; end
+ 6'o05: begin rom_output <= 16'o002020 | (1 << 12); gnstate <= 6'o06; end
6'o06: begin rom_output <= 16'o000051; gnstate <= 6'o02; end
6'o07: begin rom_output <= 16'o002020; gnstate <= 6'o10; end
6'o10: begin rom_output <= 16'o001200; gnstate <= 6'o11; end
6'o11: begin rom_output <= 16'o004020; gnstate <= 6'o12; end
- 6'o12: begin rom_output <= 16'o002100; gnstate <= 6'o13; end
+ 6'o12: begin rom_output <= 16'o002100 | (1 << 12); gnstate <= 6'o13; end
6'o13: begin rom_output <= 16'o000057; gnstate <= 6'o02; end
6'o14: begin rom_output <= 16'o004020; gnstate <= 6'o04; end
6'o15: begin rom_output <= 16'o000246; gnstate <= 6'o16; end
6'o57: begin rom_output <= 16'o004007; gnstate <= 6'o02; end
default: begin rom_output <= 16'o040000; gnstate <= 6'o20; end
endcase; // case (gostate)
- end // always @ (posedge mclk)
+ end // always @ *
always @ (posedge clk) begin
- gostate <=
- /* ga_zero_disp ? (gnstate | ga_zero) : */
- gcop_disp ? (gnstate | gcop) :
- gnstate;
+ if(clk_enable)
+ gostate <=
+ ga_zero_disp ? (gnstate | ga_zero) :
+ gcop_disp ? (gnstate | gcop) :
+ gnstate;
+ else
+ gostate <= 0;
end // always @ (posedge clk)
assign ostate = gostate;
- reg [4:0] P = 5'b0; // free storage pointer begins at 0
- reg [7:0] Q;
- reg [7:0] R;
- reg [7:0] S;
-
- reg [4:0] A; // latched address
-
- wire [7:0] I;
+ reg [12:0] P;
+ reg [15:0] Q;
+ reg [15:0] R;
+ reg [15:0] S;
- wire [7:0] G;
+ reg [12:0] A; // latched address
- /*
- assign G = rdR ? R : 8'bzzzzzzzz;
- assign G = rdQ ? Q : 8'bzzzzzzzz;
- assign G = rdP ? {3'b0, P} : 8'bzzzzzzzz;
- assign G = rdP_plus ? {3'b0, P+1} : 8'bzzzzzzzz;
- assign G = conn_i ? I : 8'bzzzzzzzz;
- assign G[4:0] = conn_ea ? E[4:0] : 5'bzzzzz;
- assign G[7:5] = conn_et ? E[7:5] : 3'bzzz;
+ assign freeptr = P;
+ assign ram_addr = A;
+ assign ram_di = S;
- assign E[4:0] = conn_ea ? G[4:0] : 5'bzzzzz;
- assign E[7:5] = conn_et ? G[7:5] : 3'bzzz;
- */
+ wire [15:0] G;
+ wire [15:0] Gout;
- wire [7:0] GfromR = rdR ? R : 0;
- wire [7:0] GfromQ = rdQ ? Q : 0;
- wire [7:0] GfromP = rdP ? {3'b0, P} : 0;
- wire [7:0] GfromP_plus = rdP_plus ? {3'b0, P + 1} : 0;
- wire [7:0] GfromI = conn_i ? I : 0;
- wire [4:0] GAfromE = conn_ea ? Ein_latched[4:0] : 0;
- wire [3:0] GTfromE = conn_et ? Ein_latched[7:5] : 0;
- wire [7:0] GfromE = {GTfromE, GAfromE};
+ wire [15:0] GfromR = rdR ? R : 0;
+ wire [15:0] GfromQ = rdQ ? Q : 0;
+ wire [15:0] GfromP = rdP ? {3'b0, P} : 0;
+ wire [15:0] GfromP_plus = rdP_plus ? {3'b0, P + 1} : 0;
+ wire [15:0] GfromI = conn_i ? ram_do : 0;
+ wire [12:0] GAfromE = conn_ea ? Ein[12:0] : 0;
+ wire [2:0] GTfromE = conn_et ? Ein[15:13] : 0;
+ wire [15:0] GfromE = {GTfromE, GAfromE};
assign G = GfromR | GfromQ | GfromP | GfromP_plus | GfromI | GfromE;
+ assign Gout = GfromR | GfromQ | GfromP | GfromP_plus | GfromI;
- assign Eout[4:0] = conn_ea ? G[4:0] : 0;
- assign Eout[7:5] = conn_et ? G[7:5] : 0;
-
- generic_dpram #(.aw(5), .dw(8)) RAM
- ( .rclk(mclk),
- .wclk(mclk),
- .rrst(1'b0),
- .wrst(1'b0),
- .rce(1'b1),
- .wce(1'b1),
-
- .oe(1'b1),
- .we(write),
- .raddr(A),
- .waddr(A),
- .do(I),
- .di(S));
+ assign Eout[12:0] = conn_ea ? Gout[12:0] : 0;
+ assign Eout[15:13] = conn_et ? Gout[15:13] : 0;
always @ (posedge clk) begin
- if (ldS) S = G;
- if (ldP) P <= G[4:0];
- if (ldR) R <= G;
- if (ldQ) Q <= G;
- if (adr) A <= S[4:0];
+ if(clk_enable) begin
+ if (ldS) S = G;
+ if (ldP) P <= G[12:0];
+ if (ldR) R <= G;
+ if (ldQ) Q <= G;
+ if (adr) A <= S[12:0];
+ end
end
endmodule // GC
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