module GCRAM
-(input clk, input we, input[5:0] addr, input[7:0] di, output reg [7:0] do, output reg [7:0] result);
- reg [7:0] mem [(1<<5)-1:0];
+(input clk, input we, input[12:0] addr, input[15:0] di, output reg [15:0] do, output reg [15:0] result);
+ reg [15:0] mem [255:0];
always @ (posedge clk)
do <= #1 mem[addr];
initial begin
mem[0] <= 0;
mem[1] <= 0;
- mem[2] <= 8'b00100000;
- mem[3] <= 8'b00100000;
- mem[4] <= 8'd8;
- mem[5] <= 8'b11101000; /* QUOTE 8 */
+ mem[2] <= 16'b0010000000000000;
+ mem[3] <= 16'b0010000000000000;
+ mem[4] <= 16'd8;
+ mem[5] <= 16'b1110000000001000; /* QUOTE 8 */
mem[6] <= 0;
- mem[7] <= 8'd49;
- mem[8] <= 8'd49;
- mem[9] <= 8'd49;
+ mem[7] <= 16'd48;
+ mem[8] <= 16'd49;
+ mem[9] <= 16'd50;
end
endmodule