One clock is enough

[clump.git] / lisp_processor.v

diff --git a/lisp_processor.v b/lisp_processor.v
index 7be974bcb1bc99c85ff76b277fee60cfbe12cdba..2ae446f753538e951589853f90e26fd9fbbf08be 100644 (file)
--- a/lisp_processor.v
+++ b/lisp_processor.v
@@ -34,8 +34,8 @@ module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx);
 
    reg [1:0]  counter = 0;
 
-   wire gc_clock = counter[1] & !initial_reset;
-   wire eval_clock = !counter[1] & step_eval & !initial_reset;
+   wire gc_clock_enable   = counter[0] &  counter[1] & !initial_reset;
+   wire eval_clock_enable = counter[0] & !counter[1] & step_eval & !initial_reset;
 
    always @ (posedge clk)
         counter <= counter + 1;
@@ -57,9 +57,9 @@ module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx);
 
    GCRAM gcram (.clk(clk), .we(ram_we), .addr(ram_addr), .di(ram_di), .do(ram_do), .result(result));
 
-   GC gc (.clk(gc_clock), .mclk(clk), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(ram_we), .ram_addr(ram_addr), .ram_di(ram_di), .ram_do(ram_do));
+   GC gc (.clk(clk), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(ram_we), .ram_addr(ram_addr), .ram_di(ram_di), .ram_do(ram_do));
 
-   EVAL eval (.clk(eval_clock), .mclk(clk), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et));
+   EVAL eval (.clk(clk), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et));
 
    // UART outputs
    wire       uart_rx_signal;