Better writer and faster UART

[clump.git] / lisp_processor.v

diff --git a/lisp_processor.v b/lisp_processor.v
index fc71e7488c18078e62deff0244a31fd36346eddb..2ffb4cafd6b0d065392bb678f68b0423a7381d5b 100644 (file)
--- a/lisp_processor.v
+++ b/lisp_processor.v
@@ -30,7 +30,7 @@
 `ifdef SIM
  `define UART_DIVIDE 1
 `else
- `define UART_DIVIDE 39
+ `define UART_DIVIDE 625
 `endif
 
 module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx);
@@ -45,10 +45,12 @@ module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx);
 
    wire gc_clock_enable   = counter[0] &  counter[1] & !reset;
    wire eval_clock_enable = counter[0] & !counter[1] & step_eval & !reset;
+   wire writer_clock_enable = counter[0] & counter[1] & writer_active;
 
    always @ (posedge clk)
         counter <= counter + 1;
 
+   wire [12:0] P;
    wire [15:0] E1;
    wire [15:0] E2;
    wire [3:0] gcop;
@@ -72,24 +74,23 @@ module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx);
    wire           reader_active;
 
    wire        ram_we = reader_active ? reader_ram_we : gc_ram_we;
-   wire [12:0] ram_addr = reader_active ? reader_ram_addr : writer_clock_enable ? writer_ram_addr : gc_ram_addr;
+   wire [12:0] ram_addr = reader_active ? reader_ram_addr : writer_active ? writer_ram_addr : gc_ram_addr;
    wire [15:0] ram_di = reader_active ? reader_ram_di : gc_ram_di;
    wire [15:0] ram_do;
 
-   reg                    writer_clock_enable = 0;
    wire                   writer_finished;
-   reg                    will_stop_writer = 0;
    reg                    writer_started = 0;
+   reg                    writer_active = 0;
 
-   GCRAM gcram (.clk(clk), .we(ram_we), .addr(ram_addr), .di(ram_di), .do(ram_do), .result(result));
+   GCRAM gcram (.clk(clk), .we(ram_we), .addr(ram_addr), .di(ram_di), .do(ram_do));
 
-   GC gc (.clk(clk), .rst(reset), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(gc_ram_we), .ram_addr(gc_ram_addr), .ram_di(gc_ram_di), .ram_do(ram_do));
+   GC gc (.clk(clk), .rst(reset), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(gc_ram_we), .ram_addr(gc_ram_addr), .ram_di(gc_ram_di), .ram_do(ram_do), .Pout(P));
 
    EVAL eval (.clk(clk), .rst(reset), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et));
 
    READER reader (.clk(clk), .clk_enable(!initial_reset), .uart_rx_byte(uart_rx_byte), .uart_rx_signal(uart_rx_signal), .uart_is_receiving(uart_is_receiving), .active(reader_active), .ram_we(reader_ram_we), .ram_addr(reader_ram_addr), .ram_di(reader_ram_di));
 
-   WRITER writer (.clk(clk), .clk_enable(writer_clock_enable), .uart_tx_byte(uart_tx_byte), .uart_tx_signal(uart_tx_signal), .uart_is_transmitting(uart_is_transmitting), .finished(writer_finished), .result(result));
+   WRITER writer (.clk(clk), .clk_enable(writer_clock_enable), .uart_tx_byte(uart_tx_byte), .uart_tx_signal(uart_tx_signal), .uart_is_transmitting(uart_is_transmitting), .finished(writer_finished), .ram_addr(writer_ram_addr), .ram_do(ram_do), .P(P));
 
    // UART outputs
    wire       uart_rx_signal;
@@ -104,25 +105,22 @@ module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx);
 
    always @ (posedge clk) begin
          if(writer_finished)
-               will_stop_writer <= 1;
-         if(will_stop_writer)
-               writer_clock_enable <= 0;
+               writer_active <= 0;
 
          if(reader_active) begin
                 writer_started <= 0;
-                will_stop_writer <= 0;
          end else if(eostate == 5'd7 && !writer_started) begin
                 writer_started <= 1;
-                writer_clock_enable <= 1;
+                writer_active <= 1;
          end
    end
 
-   // 300 baud uart
+   // 4800 baud uart
    uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error));
 
    // Assign the outputs
    assign led[0] = eval_clock_enable;
    assign led[1] = uart_is_transmitting;
    assign led[2] = uart_is_receiving;
-   assign led[3] = writer_clock_enable;
+   assign led[4] = !reset;
 endmodule