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[clump.git] / lisp_processor.v

diff --git a/lisp_processor.v b/lisp_processor.v
index fbc44673d5f9961a5cb7b20e37ba3bfcc1b79cba..6e27c792a27bb98d430c5b357f30a944c9c31f30 100644 (file)
--- a/lisp_processor.v
+++ b/lisp_processor.v
@@ -26,7 +26,7 @@
 `ifdef SIM
  `define UART_DIVIDE 1
 `else
- `define UART_DIVIDE 625
+ `define UART_DIVIDE 3
 `endif
 
 module cpu (input CLKin, output [4:0] led, output uart_tx, input uart_rx);
@@ -74,7 +74,7 @@ module cpu (input CLKin, output [4:0] led, output uart_tx, input uart_rx);
 
    GCRAM gcram (.clk(clk), .we(ram_we), .addr(ram_addr), .di(ram_di), .do(ram_do));
 
-   GC gc (.clk(clk), .rst(reset), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(gc_ram_we), .ram_addr(gc_ram_addr), .ram_di(gc_ram_di), .ram_do(ram_do), .freeptr(freeptr));
+   GC gc (.clk(clk), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(gc_ram_we), .ram_addr(gc_ram_addr), .ram_di(gc_ram_di), .ram_do(ram_do), .freeptr(freeptr));
 
    EVAL eval (.clk(clk), .rst(reset), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et), .eval_finished(eval_finished));