-`include "asciihex.v"
-`include "generic_fifo_sc_a.v"
+`include "pll.v"
`include "gc.v"
`include "eval.v"
-`include "ram.v"
-`include "rom.v"
-`include "prescaler.v"
-`include "single_trigger.v"
+`include "reader.v"
`include "uart.v"
+`include "writer.v"
+`include "controller.v"
`define GCOP_NOP 4'd0
`define GCOP_CDR 4'd1
`define GCOP_RDQA 4'd14
`define GCOP_RDQCDRRX 4'd15
-module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx);
- wire [7:0] result;
+`ifdef SIM
+ `define UART_DIVIDE 1
+`else
+ `define UART_DIVIDE 3
+`endif
- reg [1:0] counter = 0;
+module cpu (input CLKin, output [4:0] led, output uart_tx, input uart_rx);
+ wire clk;
- reg gc_clock = counter[1];
- wire eval_clock = !counter[1] & step_eval;
+ pll pll (.clock_in(CLKin), .clock_out(clk));
- always @ (posedge clk)
- counter <= counter + 1;
-
- wire [7:0] E1;
- wire [7:0] E2;
+ wire [12:0] freeptr;
+ wire [15:0] E1;
+ wire [15:0] E2;
wire [3:0] gcop;
wire [5:0] gostate;
wire [5:0] eostate;
wire step_eval;
- GC gc (.clk(gc_clock), .mclk(clk), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .result(result));
+ wire gc_ram_we;
+ wire [12:0] gc_ram_addr;
+ wire [15:0] gc_ram_di;
+
+ wire reader_ram_we;
+ wire [12:0] reader_ram_addr;
+ wire [15:0] reader_ram_di;
+
+ wire [12:0] writer_ram_addr;
+
+ wire ram_we;
+ wire [12:0] ram_addr;
+ wire [15:0] ram_di;
+ wire [15:0] ram_do;
+
+ wire eval_finished;
+ wire reader_finished;
+ wire writer_finished;
+
+ wire gc_clock_enable;
+ wire eval_clock_enable;
+ wire reader_clock_enable;
+ wire writer_clock_enable;
+ wire reset;
+
+ CTRL ctrl (.clk(clk), .step_eval(step_eval), .reader_finished(reader_finished), .eval_finished(eval_finished), .writer_finished(writer_finished), .gc_clock_enable(gc_clock_enable), .eval_clock_enable(eval_clock_enable), .reader_clock_enable(reader_clock_enable), .writer_clock_enable(writer_clock_enable), .reset(reset), .gc_ram_we(gc_ram_we), .reader_ram_we(reader_ram_we), .gc_ram_addr(gc_ram_addr), .reader_ram_addr(reader_ram_addr), .writer_ram_addr(writer_ram_addr), .gc_ram_di(gc_ram_di), .reader_ram_di(reader_ram_di), .ram_we(ram_we), .ram_addr(ram_addr), .ram_di(ram_di), .uart_is_receiving(uart_is_receiving), .uart_is_transmitting(uart_is_transmitting), .led(led));
- EVAL eval (.clk(eval_clock), .mclk(clk), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et));
+ GCRAM gcram (.clk(clk), .we(ram_we), .addr(ram_addr), .di(ram_di), .do(ram_do));
+
+ GC gc (.clk(clk), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(gc_ram_we), .ram_addr(gc_ram_addr), .ram_di(gc_ram_di), .ram_do(ram_do), .freeptr(freeptr));
+
+ EVAL eval (.clk(clk), .rst(reset), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et), .eval_finished(eval_finished));
+
+ READER reader (.clk(clk), .clk_enable(reader_clock_enable), .rx_byte(uart_rx_byte), .rx_signal(uart_rx_signal), .finished(reader_finished), .ram_we(reader_ram_we), .ram_addr(reader_ram_addr), .ram_di(reader_ram_di));
+
+ WRITER writer (.clk(clk), .clk_enable(writer_clock_enable), .tx_byte(uart_tx_byte), .tx_signal(uart_tx_signal), .tx_busy(uart_is_transmitting), .finished(writer_finished), .ram_addr(writer_ram_addr), .ram_do(ram_do), .freeptr(freeptr));
// UART outputs
wire uart_rx_signal;
wire uart_is_transmitting;
wire uart_rx_error;
- // Input logic
- wire [3:0] fifo_in;
- wire [3:0] fifo_out;
- wire fifo_full;
- wire fifo_empty;
- wire fifo_re = 0;//eval_clock & inst == `INST_READ & !fifo_empty;
- wire fifo_we = uart_rx_signal & !fifo_full;
-
- ascii_to_hex a2h (.ascii({1'b0, uart_rx_byte[6:0]}), .hex(fifo_in));
-
- generic_fifo_sc_a #(.dw(4), .aw(4)) fifo
- (.clk(clk),
- .rst(1'b1),
- .re(fifo_re),
- .we(fifo_we),
- .din(fifo_in),
- .dout(fifo_out),
- .full(fifo_full),
- .empty(fifo_empty));
-
// UART logic
- reg uart_tx_signal = 1;
- wire [7:0] uart_tx_byte = result;
-
- // 300 baud uart
- uart #(.CLOCK_DIVIDE(39)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error));
+ wire uart_tx_signal;
+ wire [7:0] uart_tx_byte;
- // Assign the outputs
- assign led[0] = eval_clock;
- assign led[1] = uart_is_transmitting;
- assign led[2] = uart_is_receiving;
- assign led[3] = recv_error;
+ // 19200 baud uart
+ uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error));
endmodule
projects / clump.git / blobdiff