Make words 16 bits wide

[clump.git] / lisp_processor.v

diff --git a/lisp_processor.v b/lisp_processor.v
index fbcca7e0cdb814d67e1ddbfda503a0741685e64d..827fbc7d0eb5a1856e2f40d240a005b2ad3d3488 100644 (file)
--- a/lisp_processor.v
+++ b/lisp_processor.v
@@ -26,18 +26,22 @@
 `define GCOP_RDQCDRRX 4'd15
 
 module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx);
-   wire [7:0] result;
+   wire [15:0] result;
+
+   reg [5:0]   initial_reset = 30;
+   always @ (posedge clk)
+        if (initial_reset) initial_reset <= initial_reset - 1;
 
    reg [1:0]  counter = 0;
 
-   reg gc_clock = counter[1];
-   wire eval_clock = !counter[1] & step_eval;
+   wire gc_clock = counter[1] & !initial_reset;
+   wire eval_clock = !counter[1] & step_eval & !initial_reset;
 
    always @ (posedge clk)
         counter <= counter + 1;
 
-   wire [7:0] E1;
-   wire [7:0] E2;
+   wire [15:0] E1;
+   wire [15:0] E2;
    wire [3:0] gcop;
    wire [5:0] gostate;
    wire [5:0] eostate;
@@ -79,7 +83,7 @@ module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx);
 
    // UART logic
    reg       uart_tx_signal = 1;
-   wire [7:0] uart_tx_byte = result;
+   wire [7:0] uart_tx_byte = result[7:0];
 
    // 300 baud uart
    uart #(.CLOCK_DIVIDE(39)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error));