-`include "asciihex.v"
-`include "generic_fifo_sc_a.v"
`include "gc.v"
`include "eval.v"
-`include "ram.v"
`include "reader.v"
-`include "rom.v"
-`include "prescaler.v"
-`include "single_trigger.v"
`include "uart.v"
`include "writer.v"
`define UART_DIVIDE 625
`endif
-module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx);
+module cpu (input clk, output [4:0] led, output uart_tx, input uart_rx);
wire [15:0] result;
reg [5:0] initial_reset = 30;