`include "gc.v"
`include "eval.v"
`include "ram.v"
+`include "reader.v"
`include "rom.v"
`include "prescaler.v"
`include "single_trigger.v"
`include "uart.v"
+`include "writer.v"
`define GCOP_NOP 4'd0
`define GCOP_CDR 4'd1
`define GCOP_RDQA 4'd14
`define GCOP_RDQCDRRX 4'd15
+`ifdef SIM
+ `define UART_DIVIDE 1
+`else
+ `define UART_DIVIDE 39
+`endif
+
module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx);
wire [15:0] result;
always @ (posedge clk)
if (initial_reset) initial_reset <= initial_reset - 1;
+ wire reset = |initial_reset || reader_active || writer_clock_enable;
reg [1:0] counter = 0;
- wire gc_clock_enable = counter[0] & counter[1] & !initial_reset;
- wire eval_clock_enable = counter[0] & !counter[1] & step_eval & !initial_reset;
+ wire gc_clock_enable = counter[0] & counter[1] & !reset;
+ wire eval_clock_enable = counter[0] & !counter[1] & step_eval & !reset;
always @ (posedge clk)
counter <= counter + 1;
wire step_eval;
- wire ram_we;
- wire [12:0] ram_addr;
- wire [15:0] ram_di;
+ wire gc_ram_we;
+ wire [12:0] gc_ram_addr;
+ wire [15:0] gc_ram_di;
+
+ wire reader_ram_we;
+ wire [12:0] reader_ram_addr;
+ wire [15:0] reader_ram_di;
+
+ wire [12:0] writer_ram_addr;
+
+ wire reader_active;
+
+ wire ram_we = reader_active ? reader_ram_we : gc_ram_we;
+ wire [12:0] ram_addr = reader_active ? reader_ram_addr : writer_clock_enable ? writer_ram_addr : gc_ram_addr;
+ wire [15:0] ram_di = reader_active ? reader_ram_di : gc_ram_di;
wire [15:0] ram_do;
+ reg writer_clock_enable = 0;
+ wire writer_finished;
+ reg will_stop_writer = 0;
+ reg writer_started = 0;
+
GCRAM gcram (.clk(clk), .we(ram_we), .addr(ram_addr), .di(ram_di), .do(ram_do), .result(result));
- GC gc (.clk(clk), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(ram_we), .ram_addr(ram_addr), .ram_di(ram_di), .ram_do(ram_do));
+ GC gc (.clk(clk), .rst(reset), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(gc_ram_we), .ram_addr(gc_ram_addr), .ram_di(gc_ram_di), .ram_do(ram_do));
+
+ EVAL eval (.clk(clk), .rst(reset), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et));
- EVAL eval (.clk(clk), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et));
+ READER reader (.clk(clk), .clk_enable(!initial_reset), .uart_rx_byte(uart_rx_byte), .uart_rx_signal(uart_rx_signal), .uart_is_receiving(uart_is_receiving), .active(reader_active), .ram_we(reader_ram_we), .ram_addr(reader_ram_addr), .ram_di(reader_ram_di));
+
+ WRITER writer (.clk(clk), .clk_enable(writer_clock_enable), .uart_tx_byte(uart_tx_byte), .uart_tx_signal(uart_tx_signal), .uart_is_transmitting(uart_is_transmitting), .finished(writer_finished), .result(result));
// UART outputs
wire uart_rx_signal;
wire uart_is_transmitting;
wire uart_rx_error;
- // Input logic
- wire [3:0] fifo_in;
- wire [3:0] fifo_out;
- wire fifo_full;
- wire fifo_empty;
- wire fifo_re = 0;//eval_clock & inst == `INST_READ & !fifo_empty;
- wire fifo_we = uart_rx_signal & !fifo_full;
-
- ascii_to_hex a2h (.ascii({1'b0, uart_rx_byte[6:0]}), .hex(fifo_in));
-
- generic_fifo_sc_a #(.dw(4), .aw(4)) fifo
- (.clk(clk),
- .rst(1'b1),
- .re(fifo_re),
- .we(fifo_we),
- .din(fifo_in),
- .dout(fifo_out),
- .full(fifo_full),
- .empty(fifo_empty));
-
// UART logic
- reg uart_tx_signal = 1;
- wire [7:0] uart_tx_byte = result[7:0];
+ wire uart_tx_signal;
+ wire [7:0] uart_tx_byte;
+
+ always @ (posedge clk) begin
+ if(writer_finished)
+ will_stop_writer <= 1;
+ if(will_stop_writer)
+ writer_clock_enable <= 0;
+
+ if(reader_active) begin
+ writer_started <= 0;
+ will_stop_writer <= 0;
+ end else if(eostate == 5'd7 && !writer_started) begin
+ writer_started <= 1;
+ writer_clock_enable <= 1;
+ end
+ end
// 300 baud uart
- uart #(.CLOCK_DIVIDE(39)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error));
+ uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error));
// Assign the outputs
- assign led[0] = eval_clock;
+ assign led[0] = eval_clock_enable;
assign led[1] = uart_is_transmitting;
assign led[2] = uart_is_receiving;
- assign led[3] = recv_error;
+ assign led[3] = writer_clock_enable;
endmodule
projects / clump.git / blobdiff