Add diagrams and pictures

[clump.git] / master.v

diff --git a/master.v b/master.v
index a009ce2c74099540bddc75c6f422705042b99134..3c70e91c3a0ea5c6cda1135aa8fb95dfc51879ba 100644 (file)
--- a/master.v
+++ b/master.v
@@ -7,7 +7,7 @@
  `define UART_DIVIDE 1
  `define I2C_DIVIDE 4
 `else
- `define UART_DIVIDE 2048
+ `define UART_DIVIDE 1024
  `define I2C_DIVIDE 256
 `endif
 
@@ -36,7 +36,7 @@ module master(input CLKin, output [4:0] led, output uart_tx, input uart_rx, outp
 
    always @(posedge clk) begin
          if(busy_in)
-               dont_send <= 23'b11111111111111111111111;
+               dont_send <= 21'b111111111111111111111;
          else if(dont_send)
                dont_send <= dont_send - 1;
    end