Add diagrams and pictures

[clump.git] / reader.v

diff --git a/reader.v b/reader.v
index 2f06a8466b15bb4d4f8a5d00bcda2b382bf75c40..50cee43a0b9b34c0f7910620eb2affdc93dc9e23 100644 (file)
--- a/reader.v
+++ b/reader.v
@@ -1,55 +1,63 @@
-`define STATE_IDLE    2'd0
-`define STATE_LENGTH  2'd1
-`define STATE_READ1   2'd2
-`define STATE_READ2   2'd3
+`define STATE_IDLE     3'd0
+`define STATE_LENGTH   3'd1
+`define STATE_READ1    3'd2
+`define STATE_READ2    3'd3
+`define STATE_WRITE    3'd4
+`define STATE_FINISHED 3'd5
 
-module READER (input clk, input clk_enable, input [7:0] uart_rx_byte, input uart_rx_signal, input uart_is_receiving, output reg active, output reg ram_we, output [12:0] ram_addr, output reg [15:0] ram_di);
-   reg [1:0] state = `STATE_IDLE;
+module READER (input clk, input clk_enable, input [7:0] rx_byte, input rx_signal, output finished, output ram_we, output [12:0] ram_addr, output reg [15:0] ram_di);
+   reg [2:0] state = `STATE_IDLE;
 
-   reg [12:0] words_left = 0;
-   reg [12:0] current_index = 0;
+   reg [12:0] total_words;
+   reg [12:0] current_index;
 
    assign ram_addr = current_index;
+   assign finished = state == `STATE_FINISHED;
+   assign ram_we   = state == `STATE_WRITE;
 
    always @ (posedge clk)
         if (clk_enable) begin
-               if(!uart_rx_signal) ram_we <= 0;
-
                case(state)
                  `STATE_IDLE: begin
-                        if(uart_rx_signal) begin
-                               words_left[12:8] <= uart_rx_byte[4:0];
-                               words_left[7:0] <= 0;
+                        if(rx_signal) begin
+                               total_words[12:8] <= rx_byte[4:0];
                                current_index <= -1;
-                               active <= 1;
                                state <= `STATE_LENGTH;
-                        end else
-                          active <= 0;
+                        end
                  end
 
                  `STATE_LENGTH: begin
-                        if(uart_rx_signal) begin
-                               words_left[7:0] <= uart_rx_byte;
+                        if(rx_signal) begin
+                               total_words[7:0] <= rx_byte;
                                state <= `STATE_READ1;
                         end
                  end
 
                  `STATE_READ1: begin
-                        if(uart_rx_signal) begin
-                               ram_di[15:8] <= uart_rx_byte;
+                        if(rx_signal) begin
+                               ram_di[15:8] <= rx_byte;
                                current_index <= current_index + 1;
-                               words_left <= words_left - 1;
                                state <= `STATE_READ2;
                         end
                  end
 
                  `STATE_READ2: begin
-                        if(uart_rx_signal) begin
-                               ram_di[7:0] <= uart_rx_byte;
-                               ram_we <= 1;
-                               state <= |words_left ? `STATE_READ1 : `STATE_IDLE;
+                        if(rx_signal) begin
+                               ram_di[7:0] <= rx_byte;
+                               state <= `STATE_WRITE;
                         end
                  end
+
+                 `STATE_WRITE: begin
+                        if(current_index + 1 == total_words) begin
+                               state <= `STATE_FINISHED;
+                        end else begin
+                               state <= `STATE_READ1;
+                        end
+                 end
+
+                 `STATE_FINISHED: state <= `STATE_IDLE;
+                 default:         state <= `STATE_IDLE;
                endcase
-        end
+        end // if (clk_enable)
 endmodule