`define STATE_READ1 2'd2
`define STATE_READ2 2'd3
-module READER (input clk, input clk_enable, input [7:0] uart_rx_byte, input uart_rx_signal, input uart_is_receiving, output reg active, output reg ram_we, output [12:0] ram_addr, output reg [15:0] ram_di);
+module READER (input clk, input clk_enable, input [7:0] rx_byte, input rx_signal, output reg active, output reg ram_we, output [12:0] ram_addr, output reg [15:0] ram_di);
reg [1:0] state = `STATE_IDLE;
reg [12:0] words_left = 0;
always @ (posedge clk)
if (clk_enable) begin
- if(!uart_rx_signal) ram_we <= 0;
+ if(!rx_signal) ram_we <= 0;
case(state)
`STATE_IDLE: begin
- if(uart_rx_signal) begin
- words_left[12:8] <= uart_rx_byte[4:0];
+ if(rx_signal) begin
+ words_left[12:8] <= rx_byte[4:0];
words_left[7:0] <= 0;
current_index <= -1;
active <= 1;
end
`STATE_LENGTH: begin
- if(uart_rx_signal) begin
- words_left[7:0] <= uart_rx_byte;
+ if(rx_signal) begin
+ words_left[7:0] <= rx_byte;
state <= `STATE_READ1;
end
end
`STATE_READ1: begin
- if(uart_rx_signal) begin
- ram_di[15:8] <= uart_rx_byte;
+ if(rx_signal) begin
+ ram_di[15:8] <= rx_byte;
current_index <= current_index + 1;
words_left <= words_left - 1;
state <= `STATE_READ2;
end
`STATE_READ2: begin
- if(uart_rx_signal) begin
- ram_di[7:0] <= uart_rx_byte;
+ if(rx_signal) begin
+ ram_di[7:0] <= rx_byte;
ram_we <= 1;
state <= |words_left ? `STATE_READ1 : `STATE_IDLE;
end