always @ (posedge clk) begin
case(addr)
4'd0: data <= 8'b0001_0110; // LDI 6
- 4'd1: data <= 8'b0110_1001; // JP 9
+ 4'd1: data <= 8'b0110_0010; // JP 9
4'd2: data <= 8'b0010_0001; // ADD 1
4'd3: data <= 8'b1001_0000; // WRITE
4'd4: data <= 8'b0110_0010; // JP 2
default: data <= 8'bxxxx_xxxx;
endcase
end
-
- assign out_data = data_out_reg;
endmodule