Conway works (with sleeps)

[clump.git] / toplevel.v

diff --git a/toplevel.v b/toplevel.v
index 728fee48e28b59c6264d3d950ba6d5c6e7b14a77..f9082347b93abe6ee5236be4380a63e5b3e5b6ff 100644 (file)
--- a/toplevel.v
+++ b/toplevel.v
@@ -1,16 +1,40 @@
+`include "pll.v"
 `include "ram.v"
 `include "chip.v"
 `include "uart.v"
 
+`ifdef SIM
+ `define UART_DIVIDE 1
+`else
+ `define UART_DIVIDE 1
+ // s/192/3/ for 19200 baud uart
+`endif
+
 module toplevel (input CLKin, output [4:0] led, output uart_tx, input uart_rx);
-   wire clk = CLKin;
+   wire clk;
+   wire clk_tmp;
+
+   //pll pll (.clock_in(CLKin), .clock_out(clk));
+
+   reg [20:0] counter = 0;
+
+   reg                   clk = 0;
+
+   always @ (posedge CLKin) begin
+         if(counter == 5000) begin
+                counter <= 0;
+                clk <= 1 - clk;
+         end
+         else
+               counter <= counter + 1;
+   end
 
    wire [11:0] mem_addr;
    wire [15:0] mem_in;
    wire [15:0] mem_out;
    wire           mem_write;
 
-   RAM #(.ADDRESS_BITS(12)) ram (.clk(clk), .write(mem_write), .addr(mem_addr), .in(mem_in), .out(mem_out));
+   RAM #(.ADDRESS_BITS(8)) ram (.clk(clk), .write(mem_write), .addr(mem_addr), .in(mem_in), .out(mem_out));
 
    reg [7:0]   from_uart [3:0];
    reg [2:0]   uart_ptr = 0;
@@ -22,49 +46,73 @@ module toplevel (input CLKin, output [4:0] led, output uart_tx, input uart_rx);
 
    reg [2:0]   op = 0;
 
-   assign led = uart_ptr;
+   reg [2:0]   last_op = 0;
+
+   reg [15:0]  I;
+   reg                    CS;
 
    chip chip (.clk(clk), .op(op), .I(I), .io_pin(0), .CS(CS), .mem_in(mem_in), .mem_out(mem_out), .mem_write(mem_write));
 
    wire           received;
    wire [7:0]  rx_byte;
    reg                    transmit = 0;
-   reg  [7:0]  tx_byte;
+   reg  [7:0]  tx_byte = 0;
+   wire           is_receiving;
+   wire           is_transmitting;
+
+   // 19200 (actually 300) baud uart
+   uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .received(received), .transmit(transmit), .tx_byte(tx_byte), .rx_byte(rx_byte), .is_receiving(is_receiving), .is_transmitting(is_transmitting));
 
-   uart uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .received(received), .transmit(transmit), .tx_byte(tx_byte), .rx_byte(rx_byte));
+   assign led[0] = is_transmitting;
+   assign led[4] = received;
+//   assign led[3:1] = last_op;
 
-   reg [15:0]  rom_I [0:5];
-   reg [7:0]  rom_mem_addr [0:5];
-   reg [2:0]  rom_op [0:5];
-   reg                   rom_CS [0:5];
+   reg                    did_it = 0;
+   assign led[2] = did_it;
 
    reg [2:0]   state = 0;
 
+//   assign led[4:2] = state;
+
    always @ (posedge clk) begin
-         if (received) begin
+         if (state == 0 && received) begin
                 from_uart[uart_ptr] <= rx_byte;
                 uart_ptr <= uart_ptr + 1;
          end
 
-         if (uart_ptr == 4) begin
+         if (state == 0 && uart_ptr == 4) begin
                 op <= op_from_uart;
+                last_op <= op_from_uart;
                 uart_ptr <= 0;
+                did_it <= 1;
                 state <= 1;
          end
 
-         if (state == 1) begin
-                transmit <= 1;
-                tx_byte <= mem_in;
+         if (state == 1 && op != `OP_READ) begin
+                op <= 0;
+                state <= 0;
+         end
+
+         if (state == 1 && op == `OP_READ) begin
+                op <= 0;
                 state <= 2;
+                transmit <= 1;
+                tx_byte <= mem_out[7:0];
          end
 
-         if (state == 2) begin
+         if (state == 2 && transmit) begin
                 transmit <= 0;
-                state <= 0;
          end
 
-         if (op != 0) begin
-                op <= 0;
+         if (state == 2 && !transmit && !is_transmitting) begin
+                state <= 3;
+                transmit <= 1;
+                tx_byte <= mem_out[15:8];
+         end
+
+         if (state == 3) begin
+                transmit <= 0;
+                state <= 0;
          end
    end
 endmodule