end
wire [11:0] mem_addr;
- wire [63:0] mem_in;
- wire [63:0] mem_out;
+ wire [15:0] mem_in;
+ wire [15:0] mem_out;
wire mem_write;
RAM #(.ADDRESS_BITS(8)) ram (.clk(clk), .write(mem_write), .addr(mem_addr), .in(mem_in), .out(mem_out));
wire [2:0] op_from_uart = from_uart[3][2:0];
wire CS = from_uart[3][3];
+ /* to execute a ROUTE instruction, we send our neighbour a STOREI
+ /* instruction with the correct address and value. This is the
+ /* STOREI instruction. */
+ wire [7:0] route_storei [3:0];
+ assign route_storei[0] = mem_out[7:0];
+ assign route_storei[1] = mem_out[15:8];
+ assign route_storei[2] = from_uart[0];
+ assign route_storei[3] = 3'd4; // OP_STOREI
+
reg [2:0] op = 0;
reg [2:0] last_op = 0;
reg [15:0] I;
reg CS;
- chip chip (.clk(clk), .op(op), .I(I), .io_pin(0), .CS(CS), .mem_in(mem_in), .mem_out(mem_out), .mem_write(mem_write));
+ reg [3:0] led_out;
+
+ chip chip (.clk(clk), .op(op), .I(I), .io_pin(0), .CS(CS), .mem_in(mem_in), .mem_out(mem_out), .mem_write(mem_write), .led_out(led_out));
wire received;
wire [7:0] rx_byte;
// 19200 (actually 300) baud uart
uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .received(received), .transmit(transmit), .tx_byte(tx_byte), .rx_byte(rx_byte), .is_receiving(is_receiving), .is_transmitting(is_transmitting));
- assign led[0] = is_transmitting;
- assign led[4] = received;
-// assign led[3:1] = last_op;
-
- assign led[2] = |mem_out; // so that mem_out is used
-
- // 0 is idle
`define STATE_IDLE 0
`define STATE_PROPAGATE 1
`define STATE_EXECUTE 2
`define STATE_ROUTE 3
- reg [5:0] state = 0;
+ reg [5:0] state = `STATE_IDLE;
-// assign led[4:2] = state;
+ assign led[3:0] = led_out;
+ assign led[4] = 0;
always @ (posedge clk) begin
case(state)
transmit <= 0;
else if(uart_ptr == 4) begin
uart_ptr <= 0;
- if(op == `OP_ROUTE) begin
+ the_leds <= last_op;
+ if(last_op == `OP_ROUTE) begin
state <= `STATE_ROUTE;
end else begin
op <= last_op;
end
`STATE_ROUTE: begin
- state <= `STATE_IDLE; // for now
+ if(transmit)
+ transmit <= 0;
+ else if(uart_ptr == 4) begin
+ uart_ptr <= 0;
+ state <= `STATE_IDLE;
+ end else if(!is_transmitting && ready_in) begin
+ tx_byte <= route_storei[uart_ptr];
+ transmit <= 1;
+ uart_ptr <= uart_ptr + 1;
+ end
end
endcase
-
- /*
-
- if (state == 1 && op != `OP_READ) begin
- op <= 0;
- state <= 0;
- end
-
- if (state == 1 && op == `OP_READ) begin
- op <= 0;
- state <= 2;
- transmit <= 1;
- tx_byte <= mem_out[7:0];
- end
-
- if (state == 2 && transmit) begin
- transmit <= 0;
- end
-
- if (state == 2 && !transmit && !is_transmitting) begin
- state <= 3;
- transmit <= 1;
- tx_byte <= mem_out[15:8];
- end
-
- if (state == 3) begin
- transmit <= 0;
- state <= 0;
- end */
end
- wire ready = (state == 0 && !is_receiving);
-
- assign ready_out = ready_in & ready;
-
+// wire ready = (state == 0 && !is_receiving);
endmodule