Make words 16 bits wide

[clump.git] / yosys-sim-script

diff --git a/yosys-sim-script b/yosys-sim-script
index eae3049a4d11e22db9243864abcea405992f8dee..965efd1672ab2382a21d9c02d073ea487a6adeb7 100755 (executable)
--- a/yosys-sim-script
+++ b/yosys-sim-script
@@ -1,3 +1,3 @@
 read_verilog -sv flash.v
 prep -top top -nordff
-sim -clock CLK -vcd test.vcd -n 200
+sim -clock CLK -vcd test.vcd -n 1000