From: Marius Gavrilescu <marius@ieval.ro>
Date: Mon, 19 Mar 2018 14:25:03 +0000 (+0200)
Subject: Slightly simpler reader
X-Git-Url: http://git.ieval.ro/?p=clump.git;a=commitdiff_plain;h=6b45cddb9132729d802ad6226ad6c5cc2eb4aa53

Slightly simpler reader
---

diff --git a/reader.v b/reader.v
index 88e52e7..e96131e 100644
--- a/reader.v
+++ b/reader.v
@@ -6,7 +6,7 @@
 module READER (input clk, input clk_enable, input [7:0] rx_byte, input rx_signal, output reg finished = 0, output reg ram_we, output [12:0] ram_addr, output reg [15:0] ram_di);
    reg [1:0] state = `STATE_IDLE;
 
-   reg [12:0] words_left;
+   reg [12:0] total_words;
    reg [12:0] current_index;
 
    assign ram_addr = current_index;
@@ -18,8 +18,7 @@ module READER (input clk, input clk_enable, input [7:0] rx_byte, input rx_signal
 		case(state)
 		  `STATE_IDLE: begin
 			 if(rx_signal) begin
-				words_left[12:8] <= rx_byte[4:0];
-				words_left[7:0] <= 0;
+				total_words[12:8] <= rx_byte[4:0];
 				current_index <= -1;
 				state <= `STATE_LENGTH;
 			 end
@@ -27,7 +26,7 @@ module READER (input clk, input clk_enable, input [7:0] rx_byte, input rx_signal
 
 		  `STATE_LENGTH: begin
 			 if(rx_signal) begin
-				words_left[7:0] <= rx_byte;
+				total_words[7:0] <= rx_byte;
 				state <= `STATE_READ1;
 			 end
 		  end
@@ -36,7 +35,6 @@ module READER (input clk, input clk_enable, input [7:0] rx_byte, input rx_signal
 			 if(rx_signal) begin
 				ram_di[15:8] <= rx_byte;
 				current_index <= current_index + 1;
-				words_left <= words_left - 1;
 				state <= `STATE_READ2;
 			 end
 		  end
@@ -45,7 +43,7 @@ module READER (input clk, input clk_enable, input [7:0] rx_byte, input rx_signal
 			 if(rx_signal) begin
 				ram_di[7:0] <= rx_byte;
 				ram_we <= 1;
-				if(|words_left) begin
+				if(current_index == total_words) begin
 				   state <= `STATE_READ1;
 				end else begin
 				   state <= `STATE_IDLE;