From eb54e6d0b78c3d1c4edcc2f213f971e2e1922bac Mon Sep 17 00:00:00 2001 From: Marius Gavrilescu Date: Mon, 26 Feb 2018 11:46:46 +0000 Subject: [PATCH] Better writer and faster UART --- flash.v | 2 +- gc.v | 3 ++- gcram.v | 5 +---- lisp_processor.v | 26 +++++++++++----------- reader.v | 12 +++++------ writer.v | 56 +++++++++++++++++++++--------------------------- 6 files changed, 46 insertions(+), 58 deletions(-) diff --git a/flash.v b/flash.v index 06ca6b6..eacbce0 100644 --- a/flash.v +++ b/flash.v @@ -15,7 +15,7 @@ module top (input CLK, output [4:0] LED, output UART_TX, input UART_RX); end // Connect up the processor - PROCESSOR cpu(.clk(counter[`SCALING]), + PROCESSOR cpu(.clk(CLK), .led(LED), .uart_tx(UART_TX), .uart_rx(UART_RX)); diff --git a/gc.v b/gc.v index c29cc6d..2f94a21 100644 --- a/gc.v +++ b/gc.v @@ -1,6 +1,6 @@ `include "gcram.v" -module GC (input clk, input clk_enable, input rst, input [15:0] Ein, output [15:0] Eout, input [3:0] gcop, output [5:0] ostate, output conn_et, output conn_ea, output step_eval, output ram_we, output [12:0] ram_addr, output [15:0] ram_di, input [15:0] ram_do); +module GC (input clk, input clk_enable, input rst, input [15:0] Ein, output [15:0] Eout, input [3:0] gcop, output [5:0] ostate, output conn_et, output conn_ea, output step_eval, output ram_we, output [12:0] ram_addr, output [15:0] ram_di, input [15:0] ram_do, output [12:0] Pout); reg [15:0] rom_output; reg [5:0] gostate; reg [5:0] gnstate; @@ -105,6 +105,7 @@ module GC (input clk, input clk_enable, input rst, input [15:0] Ein, output [15: reg [12:0] A; // latched address + assign Pout = P; assign ram_addr = A; assign ram_di = S; diff --git a/gcram.v b/gcram.v index 7e618e2..6b54061 100644 --- a/gcram.v +++ b/gcram.v @@ -1,5 +1,5 @@ module GCRAM -(input clk, input we, input[12:0] addr, input[15:0] di, output reg [15:0] do, output reg [15:0] result); +(input clk, input we, input[12:0] addr, input[15:0] di, output reg [15:0] do); reg [15:0] mem [255:0]; always @ (posedge clk) @@ -9,9 +9,6 @@ module GCRAM if (we) mem[addr] <= #1 di; - always @ (posedge clk) - result <= mem[6]; - initial begin mem[ 0] <= 0; // (cdr part of NIL) mem[ 1] <= 0; // (car part of NIL) diff --git a/lisp_processor.v b/lisp_processor.v index fc71e74..2ffb4ca 100644 --- a/lisp_processor.v +++ b/lisp_processor.v @@ -30,7 +30,7 @@ `ifdef SIM `define UART_DIVIDE 1 `else - `define UART_DIVIDE 39 + `define UART_DIVIDE 625 `endif module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx); @@ -45,10 +45,12 @@ module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx); wire gc_clock_enable = counter[0] & counter[1] & !reset; wire eval_clock_enable = counter[0] & !counter[1] & step_eval & !reset; + wire writer_clock_enable = counter[0] & counter[1] & writer_active; always @ (posedge clk) counter <= counter + 1; + wire [12:0] P; wire [15:0] E1; wire [15:0] E2; wire [3:0] gcop; @@ -72,24 +74,23 @@ module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx); wire reader_active; wire ram_we = reader_active ? reader_ram_we : gc_ram_we; - wire [12:0] ram_addr = reader_active ? reader_ram_addr : writer_clock_enable ? writer_ram_addr : gc_ram_addr; + wire [12:0] ram_addr = reader_active ? reader_ram_addr : writer_active ? writer_ram_addr : gc_ram_addr; wire [15:0] ram_di = reader_active ? reader_ram_di : gc_ram_di; wire [15:0] ram_do; - reg writer_clock_enable = 0; wire writer_finished; - reg will_stop_writer = 0; reg writer_started = 0; + reg writer_active = 0; - GCRAM gcram (.clk(clk), .we(ram_we), .addr(ram_addr), .di(ram_di), .do(ram_do), .result(result)); + GCRAM gcram (.clk(clk), .we(ram_we), .addr(ram_addr), .di(ram_di), .do(ram_do)); - GC gc (.clk(clk), .rst(reset), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(gc_ram_we), .ram_addr(gc_ram_addr), .ram_di(gc_ram_di), .ram_do(ram_do)); + GC gc (.clk(clk), .rst(reset), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(gc_ram_we), .ram_addr(gc_ram_addr), .ram_di(gc_ram_di), .ram_do(ram_do), .Pout(P)); EVAL eval (.clk(clk), .rst(reset), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et)); READER reader (.clk(clk), .clk_enable(!initial_reset), .uart_rx_byte(uart_rx_byte), .uart_rx_signal(uart_rx_signal), .uart_is_receiving(uart_is_receiving), .active(reader_active), .ram_we(reader_ram_we), .ram_addr(reader_ram_addr), .ram_di(reader_ram_di)); - WRITER writer (.clk(clk), .clk_enable(writer_clock_enable), .uart_tx_byte(uart_tx_byte), .uart_tx_signal(uart_tx_signal), .uart_is_transmitting(uart_is_transmitting), .finished(writer_finished), .result(result)); + WRITER writer (.clk(clk), .clk_enable(writer_clock_enable), .uart_tx_byte(uart_tx_byte), .uart_tx_signal(uart_tx_signal), .uart_is_transmitting(uart_is_transmitting), .finished(writer_finished), .ram_addr(writer_ram_addr), .ram_do(ram_do), .P(P)); // UART outputs wire uart_rx_signal; @@ -104,25 +105,22 @@ module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx); always @ (posedge clk) begin if(writer_finished) - will_stop_writer <= 1; - if(will_stop_writer) - writer_clock_enable <= 0; + writer_active <= 0; if(reader_active) begin writer_started <= 0; - will_stop_writer <= 0; end else if(eostate == 5'd7 && !writer_started) begin writer_started <= 1; - writer_clock_enable <= 1; + writer_active <= 1; end end - // 300 baud uart + // 4800 baud uart uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error)); // Assign the outputs assign led[0] = eval_clock_enable; assign led[1] = uart_is_transmitting; assign led[2] = uart_is_receiving; - assign led[3] = writer_clock_enable; + assign led[4] = !reset; endmodule diff --git a/reader.v b/reader.v index 8386b53..2f06a84 100644 --- a/reader.v +++ b/reader.v @@ -6,7 +6,7 @@ module READER (input clk, input clk_enable, input [7:0] uart_rx_byte, input uart_rx_signal, input uart_is_receiving, output reg active, output reg ram_we, output [12:0] ram_addr, output reg [15:0] ram_di); reg [1:0] state = `STATE_IDLE; - reg [12:0] bytes_left = 0; + reg [12:0] words_left = 0; reg [12:0] current_index = 0; assign ram_addr = current_index; @@ -18,8 +18,8 @@ module READER (input clk, input clk_enable, input [7:0] uart_rx_byte, input uart case(state) `STATE_IDLE: begin if(uart_rx_signal) begin - bytes_left[12:8] <= uart_rx_byte[4:0]; - bytes_left[7:0] <= 0; + words_left[12:8] <= uart_rx_byte[4:0]; + words_left[7:0] <= 0; current_index <= -1; active <= 1; state <= `STATE_LENGTH; @@ -29,7 +29,7 @@ module READER (input clk, input clk_enable, input [7:0] uart_rx_byte, input uart `STATE_LENGTH: begin if(uart_rx_signal) begin - bytes_left[7:0] <= uart_rx_byte; + words_left[7:0] <= uart_rx_byte; state <= `STATE_READ1; end end @@ -38,7 +38,7 @@ module READER (input clk, input clk_enable, input [7:0] uart_rx_byte, input uart if(uart_rx_signal) begin ram_di[15:8] <= uart_rx_byte; current_index <= current_index + 1; - bytes_left <= bytes_left - 1; + words_left <= words_left - 1; state <= `STATE_READ2; end end @@ -47,7 +47,7 @@ module READER (input clk, input clk_enable, input [7:0] uart_rx_byte, input uart if(uart_rx_signal) begin ram_di[7:0] <= uart_rx_byte; ram_we <= 1; - state <= |bytes_left ? `STATE_READ1 : `STATE_IDLE; + state <= |words_left ? `STATE_READ1 : `STATE_IDLE; end end endcase diff --git a/writer.v b/writer.v index 7ef47ff..37f6e0a 100644 --- a/writer.v +++ b/writer.v @@ -1,14 +1,15 @@ -`define STATE_WRITE_TYPE 3'd0 -`define STATE_WRITE1 3'd1 -`define STATE_WRITE2 3'd2 -`define STATE_WRITE3 3'd3 -`define STATE_WRITE4 3'd4 +`define STATE_START 2'b00 +`define STATE_WRITE1 2'b01 +`define STATE_WRITE2 2'b10 +`define STATE_INCREMENT 2'b11 -module WRITER (input clk, input clk_enable, output [7:0] uart_tx_byte, output reg uart_tx_signal = 0, input uart_is_transmitting, output reg finished = 0, input [15:0] result); - reg [2:0] state = `STATE_WRITE_TYPE; - reg [3:0] tx_hex = 0; +module WRITER (input clk, input clk_enable, output reg [7:0] uart_tx_byte, output reg uart_tx_signal = 0, input uart_is_transmitting, output reg finished = 0, output [12:0] ram_addr, input [15:0] ram_do, input [12:0] P); + reg [1:0] state = `STATE_START; - hex_to_ascii h2a (.hex(tx_hex), .ascii(uart_tx_byte)); + reg [12:0] current_index; + reg [12:0] freeptr; + + assign ram_addr = current_index; always @ (posedge clk) if (clk_enable) begin @@ -16,19 +17,17 @@ module WRITER (input clk, input clk_enable, output [7:0] uart_tx_byte, output re uart_tx_signal <= 0; case(state) - `STATE_WRITE_TYPE: begin + `STATE_START: begin finished <= 0; - if(!uart_is_transmitting && !uart_tx_signal) begin - uart_tx_signal <= 1; - tx_hex <= {1'b0, result[15:13]}; - state <= `STATE_WRITE1; - end + current_index <= 4; + freeptr <= P; + state <= `STATE_WRITE1; end `STATE_WRITE1: begin if(!uart_is_transmitting && !uart_tx_signal) begin uart_tx_signal <= 1; - tx_hex <= {3'b0, result[12]}; + uart_tx_byte <= ram_do[15:8]; state <= `STATE_WRITE2; end end @@ -36,27 +35,20 @@ module WRITER (input clk, input clk_enable, output [7:0] uart_tx_byte, output re `STATE_WRITE2: begin if(!uart_is_transmitting && !uart_tx_signal) begin uart_tx_signal <= 1; - tx_hex <= result[11:8]; - state <= `STATE_WRITE3; + uart_tx_byte <= ram_do[7:0]; + state <= `STATE_INCREMENT; end end - `STATE_WRITE3: begin - if(!uart_is_transmitting && !uart_tx_signal) begin - uart_tx_signal <= 1; - tx_hex <= result[7:4]; - state <= `STATE_WRITE4; - end - end - - `STATE_WRITE4: begin - if(!uart_is_transmitting && !uart_tx_signal) begin - uart_tx_signal <= 1; - tx_hex <= result[3:0]; + `STATE_INCREMENT: begin + current_index <= current_index + 1; + if(current_index >= freeptr) begin finished <= 1; - state <= `STATE_WRITE_TYPE; + state <= `STATE_START; + end else begin + state <= `STATE_WRITE1; end end - endcase + endcase // case (state) end endmodule -- 2.30.2