[yule.git] / yosys-sim-script

read_verilog -sv -DSIM flash.v
prep -top top -nordff
sim -clock CLK -vcd test.vcd -n 3000
Commit	Line	Data
ab3ea03d	1	read_verilog -sv -DSIM flash.v
a051754e	2	prep -top top -nordff
ab3ea03d	3	sim -clock CLK -vcd test.vcd -n 3000