[yule.git] / yosys-sim-script

read_verilog -sv flash.v
prep -top top -nordff
sim -clock CLK -vcd test.vcd -n 200
Commit	Line	Data
a051754e MG	1	read_verilog -sv flash.v
	2	prep -top top -nordff
	3	sim -clock CLK -vcd test.vcd -n 200