| 1 | // RAM module with single input addr, input and output ports, a write enable and clock input. |
| 2 | // Data is clocked out of, and into, the RAM on positive clock edges. |
| 3 | |
| 4 | module RAM #(parameter DATA_BITS = 8, parameter ADDRESS_BITS = 4) |
| 5 | |
| 6 | (input clk, input write, input[ADDRESS_BITS-1:0] addr, input[DATA_BITS-1:0] in_data, output[DATA_BITS-1:0] out_data); |
| 7 | |
| 8 | reg [DATA_BITS-1:0] memorySpace [0:2**ADDRESS_BITS-1]; |
| 9 | |
| 10 | reg [DATA_BITS-1:0] data_out_reg; |
| 11 | |
| 12 | always @ (posedge clk) begin |
| 13 | |
| 14 | if (write) memorySpace[addr] <= in_data; |
| 15 | |
| 16 | data_out_reg <= memorySpace[addr]; |
| 17 | |
| 18 | end |
| 19 | |
| 20 | assign out_data = data_out_reg; |
| 21 | |
| 22 | endmodule |