Several cleanups

[yule.git] / eval.v

diff --git a/eval.v b/eval.v
index 355a9ffef22379193b675d792e143f071c0a4200..96cb68e2c8e865bf1da65449121c60a60495a775 100644 (file)
--- a/eval.v
+++ b/eval.v
@@ -2,13 +2,10 @@ module EVAL(input clk, input clk_enable, input rst, input [15:0] Ein, output [15
    reg [21:0] rom_output;
    reg [5:0]  eostate;
    reg [5:0]  enstate;
-   reg [15:0]  Ein_latched;
 
-   always @(posedge clk) begin
-         if(clk_enable) begin
-                Ein_latched <= Ein;
-         end
-   end
+`ifdef SIM
+   initial eostate <= 0;
+`endif
 
    wire et_lit = rom_output[21];
    wire ea_lit = rom_output[20];