`include "gcram.v"
-module GC (input clk, input mclk, input [15:0] Ein, output [15:0] Eout, input [3:0] gcop, output [5:0] ostate, output conn_et, output conn_ea, output step_eval, output [15:0] result);
+module GC (input clk, input mclk, input [15:0] Ein, output [15:0] Eout, input [3:0] gcop, output [5:0] ostate, output conn_et, output conn_ea, output step_eval, output ram_we, output [12:0] ram_addr, output [15:0] ram_di, input [15:0] ram_do);
reg [15:0] rom_output;
reg [5:0] gostate = 6'o0;
reg [5:0] gnstate;
wire ga_zero_disp = rom_output[15];
wire gcop_disp = rom_output[14];
- wire write = rom_output[13];
+ assign ram_we = rom_output[13];
wire adr = rom_output[12];
wire rdR = rom_output[11];
wire rdQ = rom_output[10];
reg [12:0] A; // latched address
- wire [15:0] I;
+ assign ram_addr = A;
+ assign ram_di = S;
wire [15:0] G;
wire [15:0] Gout;
wire [15:0] GfromQ = rdQ ? Q : 0;
wire [15:0] GfromP = rdP ? {3'b0, P} : 0;
wire [15:0] GfromP_plus = rdP_plus ? {3'b0, P + 1} : 0;
- wire [15:0] GfromI = conn_i ? I : 0;
+ wire [15:0] GfromI = conn_i ? ram_do : 0;
wire [12:0] GAfromE = conn_ea ? Ein_latched[12:0] : 0;
wire [2:0] GTfromE = conn_et ? Ein_latched[15:13] : 0;
wire [15:0] GfromE = {GTfromE, GAfromE};
assign Eout[12:0] = conn_ea ? Gout[12:0] : 0;
assign Eout[15:13] = conn_et ? Gout[15:13] : 0;
- GCRAM gcram (.clk(mclk), .we(write), .addr(A), .do(I), .di(S), .result(result));
-
always @ (posedge clk) begin
if (ldS) S = G;
if (ldP) P <= G[12:0];