Better writer and faster UART

[yule.git] / gcram.v

diff --git a/gcram.v b/gcram.v
index 7e618e276f931ff68a09170d93748dd061d6ff9b..6b5406187bf30563477d00fc93442ec580ec5d1c 100644 (file)
--- a/gcram.v
+++ b/gcram.v
@@ -1,5 +1,5 @@
 module GCRAM
-(input clk, input we, input[12:0] addr, input[15:0] di, output reg [15:0] do, output reg [15:0] result);
+(input clk, input we, input[12:0] addr, input[15:0] di, output reg [15:0] do);
    reg [15:0] mem [255:0];
 
    always @ (posedge clk)
@@ -9,9 +9,6 @@ module GCRAM
         if (we)
           mem[addr] <= #1 di;
 
-   always @ (posedge clk)
-        result <= mem[6];
-
    initial begin
          mem[ 0] <= 0;                     // (cdr part of NIL)
          mem[ 1] <= 0;                     // (car part of NIL)