Pull the gcram outside the gc

[yule.git] / lisp_processor.v

diff --git a/lisp_processor.v b/lisp_processor.v
index 827fbc7d0eb5a1856e2f40d240a005b2ad3d3488..7be974bcb1bc99c85ff76b277fee60cfbe12cdba 100644 (file)
--- a/lisp_processor.v
+++ b/lisp_processor.v
@@ -50,7 +50,14 @@ module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx);
 
    wire          step_eval;
 
-   GC gc (.clk(gc_clock), .mclk(clk), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .result(result));
+   wire        ram_we;
+   wire [12:0] ram_addr;
+   wire [15:0] ram_di;
+   wire [15:0] ram_do;
+
+   GCRAM gcram (.clk(clk), .we(ram_we), .addr(ram_addr), .di(ram_di), .do(ram_do), .result(result));
+
+   GC gc (.clk(gc_clock), .mclk(clk), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(ram_we), .ram_addr(ram_addr), .ram_di(ram_di), .ram_do(ram_do));
 
    EVAL eval (.clk(eval_clock), .mclk(clk), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et));