Now works on iCEstick

[yule.git] / rom.v

diff --git a/rom.v b/rom.v
index cd23054738c4dbe407fd5baac19b8bca95fa050d..b2aace755b997da9dcccb869838f79522fcfeb3a 100644 (file)
--- a/rom.v
+++ b/rom.v
@@ -5,7 +5,7 @@ module ROM (input clk, input [3:0] addr, output reg [7:0] data);
    always @ (posedge clk) begin
       case(addr)
                4'd0:    data <= 8'b0001_0110; // LDI 6
-               4'd1:    data <= 8'b0110_1001; // JP 9
+               4'd1:    data <= 8'b0110_0010; // JP 9
                4'd2:    data <= 8'b0010_0001; // ADD 1
                4'd3:    data <= 8'b1001_0000; // WRITE
                4'd4:    data <= 8'b0110_0010; // JP 2
@@ -23,6 +23,4 @@ module ROM (input clk, input [3:0] addr, output reg [7:0] data);
                default: data <= 8'bxxxx_xxxx;
          endcase
    end
-
-   assign out_data = data_out_reg;
 endmodule