Add repl.png and three unused files

[yule.git] / yosys-sim-script

diff --git a/yosys-sim-script b/yosys-sim-script
index eae3049a4d11e22db9243864abcea405992f8dee..10f21eca9ecd507c127ebf4655dc12afc7beca53 100755 (executable)
--- a/yosys-sim-script
+++ b/yosys-sim-script
@@ -1,3 +1,3 @@
-read_verilog -sv flash.v
-prep -top top -nordff
-sim -clock CLK -vcd test.vcd -n 200
+read_verilog -sv -DSIM lisp_processor.v
+prep -top cpu -nordff
+sim -clock clk -vcd test.vcd -n 3000