From: Marius Gavrilescu Date: Mon, 19 Feb 2018 00:27:44 +0000 (+0000) Subject: Make words 16 bits wide X-Git-Url: http://git.ieval.ro/?p=yule.git;a=commitdiff_plain;h=b5efed3aa26a11e1da3639806afea5c772fff7aa Make words 16 bits wide --- diff --git a/eval.v b/eval.v index 2509113..8aa2159 100644 --- a/eval.v +++ b/eval.v @@ -1,8 +1,8 @@ -module EVAL(input clk, input mclk, input [7:0] Ein, output [7:0] Eout, output [3:0] gcop, output [5:0] ostate, input conn_ea, input conn_et); +module EVAL(input clk, input mclk, input [15:0] Ein, output [15:0] Eout, output [3:0] gcop, output [5:0] ostate, input conn_ea, input conn_et); reg [21:0] rom_output; reg [5:0] eostate = 6'o0; reg [5:0] enstate; - reg [7:0] Ein_latched; + reg [15:0] Ein_latched; always @(posedge clk) begin Ein_latched <= Ein; @@ -26,6 +26,9 @@ module EVAL(input clk, input mclk, input [7:0] Ein, output [7:0] Eout, output [3 wire [3:0] gcop = rom_output[6:3]; wire [2:0] lit = rom_output[2:0]; + wire et_zero = ~|E[15:13]; + wire ea_zero = ~|E[12:0]; + always @* begin case(eostate) 6'o00: begin rom_output <= 22'o14004002; enstate <= 6'o01; end @@ -92,33 +95,33 @@ module EVAL(input clk, input mclk, input [7:0] Ein, output [7:0] Eout, output [3 always @ (posedge clk) begin eostate <= - et_disp ? (enstate | E[7:5]) : + et_disp ? (enstate | E[15:13]) : eaz_etz_eqv_disp ? (enstate | {ea_zero, et_zero, 1'b0}) : enstate; end assign ostate = eostate; - reg [7:0] V; - reg [7:0] X; - reg [7:0] N; - reg [7:0] L; - reg [7:0] C; + reg [15:0] V; + reg [15:0] X; + reg [15:0] N; + reg [15:0] L; + reg [15:0] C; - wire [7:0] E; + wire [15:0] E; - wire [7:0] EfromV = rdV ? V : 0; - wire [7:0] EfromX = rdX ? X : 0; - wire [7:0] EfromXp = rdXp ? {X[7:5], X[4:0] + 1} : 0; - wire [7:0] EfromN = rdN ? N : 0; - wire [7:0] EfromL = rdL ? L : 0; - wire [7:0] EfromC = rdC ? C : 0; - wire [4:0] EAfromEin = conn_ea ? Ein[4:0] : 0; - wire [3:0] ETfromEin = conn_et ? Ein[7:5] : 0; - wire [7:0] EfromEin = {ETfromEin, EAfromEin}; - wire [4:0] EAfromLIT = ea_lit ? {1'b0, lit, 1'b0} : 0; - wire [3:0] ETfromLIT = et_lit ? lit : 0; - wire [7:0] EfromLIT = {ETfromLIT, EAfromLIT}; + wire [15:0] EfromV = rdV ? V : 0; + wire [15:0] EfromX = rdX ? X : 0; + wire [15:0] EfromXp = rdXp ? {X[15:13], X[12:0] + 1} : 0; + wire [15:0] EfromN = rdN ? N : 0; + wire [15:0] EfromL = rdL ? L : 0; + wire [15:0] EfromC = rdC ? C : 0; + wire [12:0] EAfromEin = conn_ea ? Ein[12:0] : 0; + wire [2:0] ETfromEin = conn_et ? Ein[15:13] : 0; + wire [15:0] EfromEin = {ETfromEin, EAfromEin}; + wire [12:0] EAfromLIT = ea_lit ? {8'b0, lit, 1'b0} : 0; + wire [2:0] ETfromLIT = et_lit ? lit : 0; + wire [15:0] EfromLIT = {ETfromLIT, EAfromLIT}; assign E = EfromV | EfromX | EfromXp | EfromN | EfromL | EfromC | EfromLIT | EfromEin; assign Eout = EfromV | EfromX | EfromXp | EfromN | EfromL | EfromC | EfromLIT; diff --git a/gc.v b/gc.v index 682f51a..ceae7d7 100644 --- a/gc.v +++ b/gc.v @@ -1,10 +1,10 @@ `include "gcram.v" -module GC (input clk, input mclk, input [7:0] Ein, output [7:0] Eout, input [3:0] gcop, output [5:0] ostate, output conn_et, output conn_ea, output step_eval, output [7:0] result); +module GC (input clk, input mclk, input [15:0] Ein, output [15:0] Eout, input [3:0] gcop, output [5:0] ostate, output conn_et, output conn_ea, output step_eval, output [15:0] result); reg [15:0] rom_output; reg [5:0] gostate = 6'o0; reg [5:0] gnstate; - reg [7:0] Ein_latched = 6'h44; // initial value of E + reg [15:0] Ein_latched = 16'b0100000000000100; // initial value of E always @(posedge clk) begin Ein_latched <= Ein; @@ -27,7 +27,7 @@ module GC (input clk, input mclk, input [7:0] Ein, output [7:0] Eout, input [3:0 assign conn_ea = rom_output[1]; assign step_eval = rom_output[0]; - wire ga_zero = ~|G[7:5]; + wire ga_zero = ~|G[12:0]; always @* begin case(gostate) @@ -36,7 +36,7 @@ module GC (input clk, input mclk, input [7:0] Ein, output [7:0] Eout, input [3:0 6'o02: begin rom_output <= 16'o040000; gnstate <= 6'o20; end 6'o03: begin rom_output <= 16'o000126; gnstate <= 6'o04; end 6'o04: begin rom_output <= 16'o001200; gnstate <= 6'o05; end - 6'o05: begin rom_output <= 16'o002020; gnstate <= 6'o06; end + 6'o05: begin rom_output <= 16'o002020 | (1 << 12); gnstate <= 6'o06; end 6'o06: begin rom_output <= 16'o000051; gnstate <= 6'o02; end 6'o07: begin rom_output <= 16'o002020; gnstate <= 6'o10; end 6'o10: begin rom_output <= 16'o001200; gnstate <= 6'o11; end @@ -92,53 +92,40 @@ module GC (input clk, input mclk, input [7:0] Ein, output [7:0] Eout, input [3:0 assign ostate = gostate; - reg [4:0] P; - reg [7:0] Q; - reg [7:0] R; - reg [7:0] S; + reg [12:0] P; + reg [15:0] Q; + reg [15:0] R; + reg [15:0] S; - reg [4:0] A; // latched address + reg [12:0] A; // latched address - wire [7:0] I; + wire [15:0] I; - wire [7:0] G; - wire [7:0] Gout; + wire [15:0] G; + wire [15:0] Gout; - /* - assign G = rdR ? R : 8'bzzzzzzzz; - assign G = rdQ ? Q : 8'bzzzzzzzz; - assign G = rdP ? {3'b0, P} : 8'bzzzzzzzz; - assign G = rdP_plus ? {3'b0, P+1} : 8'bzzzzzzzz; - assign G = conn_i ? I : 8'bzzzzzzzz; - assign G[4:0] = conn_ea ? E[4:0] : 5'bzzzzz; - assign G[7:5] = conn_et ? E[7:5] : 3'bzzz; - - assign E[4:0] = conn_ea ? G[4:0] : 5'bzzzzz; - assign E[7:5] = conn_et ? G[7:5] : 3'bzzz; - */ - - wire [7:0] GfromR = rdR ? R : 0; - wire [7:0] GfromQ = rdQ ? Q : 0; - wire [7:0] GfromP = rdP ? {3'b0, P} : 0; - wire [7:0] GfromP_plus = rdP_plus ? {3'b0, P + 1} : 0; - wire [7:0] GfromI = conn_i ? I : 0; - wire [4:0] GAfromE = conn_ea ? Ein_latched[4:0] : 0; - wire [3:0] GTfromE = conn_et ? Ein_latched[7:5] : 0; - wire [7:0] GfromE = {GTfromE, GAfromE}; + wire [15:0] GfromR = rdR ? R : 0; + wire [15:0] GfromQ = rdQ ? Q : 0; + wire [15:0] GfromP = rdP ? {3'b0, P} : 0; + wire [15:0] GfromP_plus = rdP_plus ? {3'b0, P + 1} : 0; + wire [15:0] GfromI = conn_i ? I : 0; + wire [12:0] GAfromE = conn_ea ? Ein_latched[12:0] : 0; + wire [2:0] GTfromE = conn_et ? Ein_latched[15:13] : 0; + wire [15:0] GfromE = {GTfromE, GAfromE}; assign G = GfromR | GfromQ | GfromP | GfromP_plus | GfromI | GfromE; assign Gout = GfromR | GfromQ | GfromP | GfromP_plus | GfromI; - assign Eout[4:0] = conn_ea ? Gout[4:0] : 0; - assign Eout[7:5] = conn_et ? Gout[7:5] : 0; + assign Eout[12:0] = conn_ea ? Gout[12:0] : 0; + assign Eout[15:13] = conn_et ? Gout[15:13] : 0; GCRAM gcram (.clk(mclk), .we(write), .addr(A), .do(I), .di(S), .result(result)); always @ (posedge clk) begin if (ldS) S = G; - if (ldP) P <= G[4:0]; + if (ldP) P <= G[12:0]; if (ldR) R <= G; if (ldQ) Q <= G; - if (adr) A <= S[4:0]; + if (adr) A <= S[12:0]; end endmodule // GC diff --git a/gcram.v b/gcram.v index bb03b36..0f68a18 100644 --- a/gcram.v +++ b/gcram.v @@ -1,6 +1,6 @@ module GCRAM -(input clk, input we, input[5:0] addr, input[7:0] di, output reg [7:0] do, output reg [7:0] result); - reg [7:0] mem [(1<<5)-1:0]; +(input clk, input we, input[12:0] addr, input[15:0] di, output reg [15:0] do, output reg [15:0] result); + reg [15:0] mem [255:0]; always @ (posedge clk) do <= #1 mem[addr]; @@ -15,13 +15,13 @@ module GCRAM initial begin mem[0] <= 0; mem[1] <= 0; - mem[2] <= 8'b00100000; - mem[3] <= 8'b00100000; - mem[4] <= 8'd8; - mem[5] <= 8'b11101000; /* QUOTE 8 */ + mem[2] <= 16'b0010000000000000; + mem[3] <= 16'b0010000000000000; + mem[4] <= 16'd8; + mem[5] <= 16'b1110000000001000; /* QUOTE 8 */ mem[6] <= 0; - mem[7] <= 8'd49; - mem[8] <= 8'd49; - mem[9] <= 8'd49; + mem[7] <= 16'd48; + mem[8] <= 16'd49; + mem[9] <= 16'd50; end endmodule diff --git a/lisp_processor.v b/lisp_processor.v index fbcca7e..827fbc7 100644 --- a/lisp_processor.v +++ b/lisp_processor.v @@ -26,18 +26,22 @@ `define GCOP_RDQCDRRX 4'd15 module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx); - wire [7:0] result; + wire [15:0] result; + + reg [5:0] initial_reset = 30; + always @ (posedge clk) + if (initial_reset) initial_reset <= initial_reset - 1; reg [1:0] counter = 0; - reg gc_clock = counter[1]; - wire eval_clock = !counter[1] & step_eval; + wire gc_clock = counter[1] & !initial_reset; + wire eval_clock = !counter[1] & step_eval & !initial_reset; always @ (posedge clk) counter <= counter + 1; - wire [7:0] E1; - wire [7:0] E2; + wire [15:0] E1; + wire [15:0] E2; wire [3:0] gcop; wire [5:0] gostate; wire [5:0] eostate; @@ -79,7 +83,7 @@ module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx); // UART logic reg uart_tx_signal = 1; - wire [7:0] uart_tx_byte = result; + wire [7:0] uart_tx_byte = result[7:0]; // 300 baud uart uart #(.CLOCK_DIVIDE(39)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error)); diff --git a/yosys-sim-script b/yosys-sim-script index eae3049..965efd1 100755 --- a/yosys-sim-script +++ b/yosys-sim-script @@ -1,3 +1,3 @@ read_verilog -sv flash.v prep -top top -nordff -sim -clock CLK -vcd test.vcd -n 200 +sim -clock CLK -vcd test.vcd -n 1000