From 29d6bd4718c5788a15657813c5cad8bb82f12684 Mon Sep 17 00:00:00 2001 From: Marius Gavrilescu Date: Mon, 19 Feb 2018 14:09:05 +0000 Subject: [PATCH] One clock is enough --- eval.v | 28 +++++++++++++++++----------- gc.v | 28 +++++++++++++++++----------- lisp_processor.v | 8 ++++---- 3 files changed, 38 insertions(+), 26 deletions(-) diff --git a/eval.v b/eval.v index 8aa2159..75a979c 100644 --- a/eval.v +++ b/eval.v @@ -1,11 +1,13 @@ -module EVAL(input clk, input mclk, input [15:0] Ein, output [15:0] Eout, output [3:0] gcop, output [5:0] ostate, input conn_ea, input conn_et); +module EVAL(input clk, input clk_enable, input [15:0] Ein, output [15:0] Eout, output [3:0] gcop, output [5:0] ostate, input conn_ea, input conn_et); reg [21:0] rom_output; reg [5:0] eostate = 6'o0; reg [5:0] enstate; reg [15:0] Ein_latched; always @(posedge clk) begin - Ein_latched <= Ein; + if(clk_enable) begin + Ein_latched <= Ein; + end end wire et_lit = rom_output[21]; @@ -94,10 +96,12 @@ module EVAL(input clk, input mclk, input [15:0] Ein, output [15:0] Eout, output end // always @ * always @ (posedge clk) begin - eostate <= - et_disp ? (enstate | E[15:13]) : - eaz_etz_eqv_disp ? (enstate | {ea_zero, et_zero, 1'b0}) : - enstate; + if (clk_enable) begin + eostate <= + et_disp ? (enstate | E[15:13]) : + eaz_etz_eqv_disp ? (enstate | {ea_zero, et_zero, 1'b0}) : + enstate; + end end assign ostate = eostate; @@ -127,10 +131,12 @@ module EVAL(input clk, input mclk, input [15:0] Ein, output [15:0] Eout, output assign Eout = EfromV | EfromX | EfromXp | EfromN | EfromL | EfromC | EfromLIT; always @ (posedge clk) begin - if (ldV) V <= E; - if (ldX) X <= E; - if (ldN) N <= E; - if (ldL) L <= E; - if (ldC) C <= E; + if (clk_enable) begin + if (ldV) V <= E; + if (ldX) X <= E; + if (ldN) N <= E; + if (ldL) L <= E; + if (ldC) C <= E; + end end endmodule // EVAL diff --git a/gc.v b/gc.v index d452178..2bbada4 100644 --- a/gc.v +++ b/gc.v @@ -1,13 +1,15 @@ `include "gcram.v" -module GC (input clk, input mclk, input [15:0] Ein, output [15:0] Eout, input [3:0] gcop, output [5:0] ostate, output conn_et, output conn_ea, output step_eval, output ram_we, output [12:0] ram_addr, output [15:0] ram_di, input [15:0] ram_do); +module GC (input clk, input clk_enable, input [15:0] Ein, output [15:0] Eout, input [3:0] gcop, output [5:0] ostate, output conn_et, output conn_ea, output step_eval, output ram_we, output [12:0] ram_addr, output [15:0] ram_di, input [15:0] ram_do); reg [15:0] rom_output; reg [5:0] gostate = 6'o0; reg [5:0] gnstate; reg [15:0] Ein_latched = 16'b0100000000000100; // initial value of E always @(posedge clk) begin - Ein_latched <= Ein; + if(clk_enable) begin + Ein_latched <= Ein; + end end wire ga_zero_disp = rom_output[15]; @@ -84,10 +86,12 @@ module GC (input clk, input mclk, input [15:0] Ein, output [15:0] Eout, input [3 end // always @ * always @ (posedge clk) begin - gostate <= - ga_zero_disp ? (gnstate | ga_zero) : - gcop_disp ? (gnstate | gcop) : - gnstate; + if(clk_enable) begin + gostate <= + ga_zero_disp ? (gnstate | ga_zero) : + gcop_disp ? (gnstate | gcop) : + gnstate; + end end // always @ (posedge clk) assign ostate = gostate; @@ -121,10 +125,12 @@ module GC (input clk, input mclk, input [15:0] Ein, output [15:0] Eout, input [3 assign Eout[15:13] = conn_et ? Gout[15:13] : 0; always @ (posedge clk) begin - if (ldS) S = G; - if (ldP) P <= G[12:0]; - if (ldR) R <= G; - if (ldQ) Q <= G; - if (adr) A <= S[12:0]; + if(clk_enable) begin + if (ldS) S = G; + if (ldP) P <= G[12:0]; + if (ldR) R <= G; + if (ldQ) Q <= G; + if (adr) A <= S[12:0]; + end end endmodule // GC diff --git a/lisp_processor.v b/lisp_processor.v index 7be974b..2ae446f 100644 --- a/lisp_processor.v +++ b/lisp_processor.v @@ -34,8 +34,8 @@ module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx); reg [1:0] counter = 0; - wire gc_clock = counter[1] & !initial_reset; - wire eval_clock = !counter[1] & step_eval & !initial_reset; + wire gc_clock_enable = counter[0] & counter[1] & !initial_reset; + wire eval_clock_enable = counter[0] & !counter[1] & step_eval & !initial_reset; always @ (posedge clk) counter <= counter + 1; @@ -57,9 +57,9 @@ module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx); GCRAM gcram (.clk(clk), .we(ram_we), .addr(ram_addr), .di(ram_di), .do(ram_do), .result(result)); - GC gc (.clk(gc_clock), .mclk(clk), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(ram_we), .ram_addr(ram_addr), .ram_di(ram_di), .ram_do(ram_do)); + GC gc (.clk(clk), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(ram_we), .ram_addr(ram_addr), .ram_di(ram_di), .ram_do(ram_do)); - EVAL eval (.clk(eval_clock), .mclk(clk), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et)); + EVAL eval (.clk(clk), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et)); // UART outputs wire uart_rx_signal; -- 2.30.2