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1`define STATE_START 2'b00
2`define STATE_WRITE1 2'b01
3`define STATE_WRITE2 2'b10
4`define STATE_INCREMENT 2'b11
3f6eb730 5
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6module WRITER (input clk, input clk_enable, output reg [7:0] uart_tx_byte, output reg uart_tx_signal = 0, input uart_is_transmitting, output reg finished = 0, output [12:0] ram_addr, input [15:0] ram_do, input [12:0] P);
7 reg [1:0] state = `STATE_START;
3f6eb730 8
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9 reg [12:0] current_index;
10 reg [12:0] freeptr;
11
12 assign ram_addr = current_index;
3f6eb730 13
2155cfe3 14 always @ (posedge clk) begin
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15 if (clk_enable) begin
16 if(uart_tx_signal)
17 uart_tx_signal <= 0;
18
19 case(state)
eb54e6d0 20 `STATE_START: begin
3f6eb730 21 finished <= 0;
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22 current_index <= 4;
23 freeptr <= P;
24 state <= `STATE_WRITE1;
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25 end
26
27 `STATE_WRITE1: begin
28 if(!uart_is_transmitting && !uart_tx_signal) begin
29 uart_tx_signal <= 1;
eb54e6d0 30 uart_tx_byte <= ram_do[15:8];
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31 state <= `STATE_WRITE2;
32 end
33 end
34
35 `STATE_WRITE2: begin
36 if(!uart_is_transmitting && !uart_tx_signal) begin
37 uart_tx_signal <= 1;
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38 uart_tx_byte <= ram_do[7:0];
39 state <= `STATE_INCREMENT;
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40 end
41 end
42
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43 `STATE_INCREMENT: begin
44 current_index <= current_index + 1;
45 if(current_index >= freeptr) begin
3f6eb730 46 finished <= 1;
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47 state <= `STATE_START;
48 end else begin
49 state <= `STATE_WRITE1;
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50 end
51 end
eb54e6d0 52 endcase // case (state)
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53 end // if (clk_enable)
54 else
55 finished <= 0;
56 end
3f6eb730 57endmodule
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