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1 | `include "pll.v" | |
2 | `include "ram.v" | |
3 | `include "chip.v" | |
4 | `include "uart.v" | |
5 | ||
6 | `ifdef SIM | |
7 | `define UART_DIVIDE 1 | |
8 | `else | |
9 | `define UART_DIVIDE 1 | |
10 | // s/192/3/ for 19200 baud uart | |
11 | `endif | |
12 | ||
13 | module toplevel (input CLKin, output [4:0] led, output uart_tx, input uart_rx); | |
14 | wire clk; | |
15 | wire clk_tmp; | |
16 | ||
17 | //pll pll (.clock_in(CLKin), .clock_out(clk)); | |
18 | ||
19 | reg [20:0] counter = 0; | |
20 | ||
21 | reg clk = 0; | |
22 | ||
23 | always @ (posedge CLKin) begin | |
24 | if(counter == 5000) begin | |
25 | counter <= 0; | |
26 | clk <= 1 - clk; | |
27 | end | |
28 | else | |
29 | counter <= counter + 1; | |
30 | end | |
31 | ||
32 | wire [11:0] mem_addr; | |
33 | wire [15:0] mem_in; | |
34 | wire [15:0] mem_out; | |
35 | wire mem_write; | |
36 | ||
37 | RAM #(.ADDRESS_BITS(8)) ram (.clk(clk), .write(mem_write), .addr(mem_addr), .in(mem_in), .out(mem_out)); | |
38 | ||
39 | reg [7:0] from_uart [3:0]; | |
40 | reg [2:0] uart_ptr = 0; | |
41 | ||
42 | wire [15:0] I = {from_uart[1], from_uart[0]}; | |
43 | assign mem_addr = from_uart[2]; | |
44 | wire [2:0] op_from_uart = from_uart[3][2:0]; | |
45 | wire CS = from_uart[3][3]; | |
46 | ||
47 | reg [2:0] op = 0; | |
48 | ||
49 | reg [2:0] last_op = 0; | |
50 | ||
51 | reg [15:0] I; | |
52 | reg CS; | |
53 | ||
54 | chip chip (.clk(clk), .op(op), .I(I), .io_pin(0), .CS(CS), .mem_in(mem_in), .mem_out(mem_out), .mem_write(mem_write)); | |
55 | ||
56 | wire received; | |
57 | wire [7:0] rx_byte; | |
58 | reg transmit = 0; | |
59 | reg [7:0] tx_byte = 0; | |
60 | wire is_receiving; | |
61 | wire is_transmitting; | |
62 | ||
63 | // 19200 (actually 300) baud uart | |
64 | uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .received(received), .transmit(transmit), .tx_byte(tx_byte), .rx_byte(rx_byte), .is_receiving(is_receiving), .is_transmitting(is_transmitting)); | |
65 | ||
66 | assign led[0] = is_transmitting; | |
67 | assign led[4] = received; | |
68 | // assign led[3:1] = last_op; | |
69 | ||
70 | reg did_it = 0; | |
71 | assign led[2] = did_it; | |
72 | ||
73 | reg [2:0] state = 0; | |
74 | ||
75 | // assign led[4:2] = state; | |
76 | ||
77 | always @ (posedge clk) begin | |
78 | if (state == 0 && received) begin | |
79 | from_uart[uart_ptr] <= rx_byte; | |
80 | uart_ptr <= uart_ptr + 1; | |
81 | end | |
82 | ||
83 | if (state == 0 && uart_ptr == 4) begin | |
84 | op <= op_from_uart; | |
85 | last_op <= op_from_uart; | |
86 | uart_ptr <= 0; | |
87 | did_it <= 1; | |
88 | state <= 1; | |
89 | end | |
90 | ||
91 | if (state == 1 && op != `OP_READ) begin | |
92 | op <= 0; | |
93 | state <= 0; | |
94 | end | |
95 | ||
96 | if (state == 1 && op == `OP_READ) begin | |
97 | op <= 0; | |
98 | state <= 2; | |
99 | transmit <= 1; | |
100 | tx_byte <= mem_out[7:0]; | |
101 | end | |
102 | ||
103 | if (state == 2 && transmit) begin | |
104 | transmit <= 0; | |
105 | end | |
106 | ||
107 | if (state == 2 && !transmit && !is_transmitting) begin | |
108 | state <= 3; | |
109 | transmit <= 1; | |
110 | tx_byte <= mem_out[15:8]; | |
111 | end | |
112 | ||
113 | if (state == 3) begin | |
114 | transmit <= 0; | |
115 | state <= 0; | |
116 | end | |
117 | end | |
118 | endmodule |