10 // s/192/3/ for 19200 baud uart
13 module toplevel (input CLKin, output [4:0] led, output uart_tx, input uart_rx);
17 //pll pll (.clock_in(CLKin), .clock_out(clk));
19 reg [20:0] counter = 0;
23 always @ (posedge CLKin) begin
24 if(counter == 5000) begin
29 counter <= counter + 1;
37 RAM #(.ADDRESS_BITS(8)) ram (.clk(clk), .write(mem_write), .addr(mem_addr), .in(mem_in), .out(mem_out));
39 reg [7:0] from_uart [3:0];
40 reg [2:0] uart_ptr = 0;
42 wire [15:0] I = {from_uart[1], from_uart[0]};
43 assign mem_addr = from_uart[2];
44 wire [2:0] op_from_uart = from_uart[3][2:0];
45 wire CS = from_uart[3][3];
49 reg [2:0] last_op = 0;
54 chip chip (.clk(clk), .op(op), .I(I), .io_pin(0), .CS(CS), .mem_in(mem_in), .mem_out(mem_out), .mem_write(mem_write));
59 reg [7:0] tx_byte = 0;
63 // 19200 (actually 300) baud uart
64 uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .received(received), .transmit(transmit), .tx_byte(tx_byte), .rx_byte(rx_byte), .is_receiving(is_receiving), .is_transmitting(is_transmitting));
66 assign led[0] = is_transmitting;
67 assign led[4] = received;
68 // assign led[3:1] = last_op;
71 assign led[2] = did_it;
75 // assign led[4:2] = state;
77 always @ (posedge clk) begin
78 if (state == 0 && received) begin
79 from_uart[uart_ptr] <= rx_byte;
80 uart_ptr <= uart_ptr + 1;
83 if (state == 0 && uart_ptr == 4) begin
85 last_op <= op_from_uart;
91 if (state == 1 && op != `OP_READ) begin
96 if (state == 1 && op == `OP_READ) begin
100 tx_byte <= mem_out[7:0];
103 if (state == 2 && transmit) begin
107 if (state == 2 && !transmit && !is_transmitting) begin
110 tx_byte <= mem_out[15:8];
113 if (state == 3) begin