2 (input clk, input we, input[12:0] addr, input[15:0] di, output reg [15:0] do, output reg [15:0] result);
3 reg [15:0] mem [255:0];
12 always @ (posedge clk)
18 mem[2] <= 16'b0010000000000000;
19 mem[3] <= 16'b0010000000000000;
21 mem[5] <= 16'b1110000000001000; /* QUOTE 8 */