2 `include "generic_fifo_sc_a.v"
8 `include "single_trigger.v"
14 `define GCOP_CDRQ 4'd3
15 `define GCOP_CARQ 4'd4
16 `define GCOP_CARR 4'd5
17 `define GCOP_CDRRX 4'd6
18 `define GCOP_CARRX 4'd7
19 `define GCOP_CDRQX 4'd8
20 `define GCOP_CONS 4'd9
21 `define GCOP_XCONS 4'd10
22 `define GCOP_RPLACDR 4'd11
23 `define GCOP_LDQ 4'd12
24 `define GCOP_RDQ 4'd13
25 `define GCOP_RDQA 4'd14
26 `define GCOP_RDQCDRRX 4'd15
28 module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx);
31 reg [5:0] initial_reset = 30;
32 always @ (posedge clk)
33 if (initial_reset) initial_reset <= initial_reset - 1;
35 reg [1:0] counter = 0;
37 wire gc_clock = counter[1] & !initial_reset;
38 wire eval_clock = !counter[1] & step_eval & !initial_reset;
40 always @ (posedge clk)
41 counter <= counter + 1;
53 GC gc (.clk(gc_clock), .mclk(clk), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .result(result));
55 EVAL eval (.clk(eval_clock), .mclk(clk), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et));
59 wire [7:0] uart_rx_byte;
60 wire uart_is_receiving;
61 wire uart_is_transmitting;
69 wire fifo_re = 0;//eval_clock & inst == `INST_READ & !fifo_empty;
70 wire fifo_we = uart_rx_signal & !fifo_full;
72 ascii_to_hex a2h (.ascii({1'b0, uart_rx_byte[6:0]}), .hex(fifo_in));
74 generic_fifo_sc_a #(.dw(4), .aw(4)) fifo
85 reg uart_tx_signal = 1;
86 wire [7:0] uart_tx_byte = result[7:0];
89 uart #(.CLOCK_DIVIDE(39)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error));
92 assign led[0] = eval_clock;
93 assign led[1] = uart_is_transmitting;
94 assign led[2] = uart_is_receiving;
95 assign led[3] = recv_error;