Proper macros for simulation/normal running

diff --git a/flash.v b/flash.v
index 59a472e208a72a7a91c01786a803a0ad145de713..06ca6b6d7b4646c355b64082cdd11f0e913ad71c 100644 (file)
--- a/flash.v
+++ b/flash.v
@@ -1,5 +1,11 @@
 `include "lisp_processor.v"
 
+`ifdef SIM
+`define SCALING 0
+`else
+`define SCALING 7
+`endif
+
 module top (input CLK, output [4:0] LED, output UART_TX, input UART_RX);
    // Prescaler on the clock
    reg [24:0]  counter = 0;
@@ -9,7 +15,7 @@ module top (input CLK, output [4:0] LED, output UART_TX, input UART_RX);
    end
 
    // Connect up the processor
-   PROCESSOR cpu(.clk(counter[7]),
+   PROCESSOR cpu(.clk(counter[`SCALING]),
                                 .led(LED),
                                 .uart_tx(UART_TX),
                                 .uart_rx(UART_RX));

diff --git a/gcram.v b/gcram.v
index 0f68a18652b3e188750a28ce7e86debe954f4ee7..7e618e276f931ff68a09170d93748dd061d6ff9b 100644 (file)
--- a/gcram.v
+++ b/gcram.v
@@ -13,15 +13,17 @@ module GCRAM
         result <= mem[6];
 
    initial begin
-         mem[0] <= 0;
-         mem[1] <= 0;
-         mem[2] <= 16'b0010000000000000;
-         mem[3] <= 16'b0010000000000000;
-         mem[4] <= 16'd8;
-         mem[5] <= 16'b1110000000001000; /* QUOTE 8 */
-         mem[6] <= 0;
-         mem[7] <= 16'd48;
-         mem[8] <= 16'd49;
-         mem[9] <= 16'd50;
+         mem[ 0] <= 0;                     // (cdr part of NIL)
+         mem[ 1] <= 0;                     // (car part of NIL)
+         mem[ 2] <= 16'b0010000000000000;  // (cdr part of T)
+         mem[ 3] <= 16'b0010000000000000;  // (car part of T)
+         mem[ 4] <= 16'd12;                // (free storage pointer)
+         mem[ 5] <= 16'b1100000000000111;  // CALL 7
+         mem[ 6] <= 0;                     // (result of computation)
+         mem[ 7] <= 16'b0000000000001001;  // MORE 9
+         mem[ 8] <= 16'b0010000000000101;  // NUMBER 5
+         mem[ 9] <= 16'b1110000000000000;  // FUNCALL NIL
+         mem[10] <= 16'b1000000000001011;  // PROC 11
+         mem[11] <= 16'b0101111111111110;  // VAR -2
    end
 endmodule

diff --git a/yosys-sim-script b/yosys-sim-script
index 965efd1672ab2382a21d9c02d073ea487a6adeb7..9cffede952a7db8d46e6e4a9b1e7a326590ea9ec 100755 (executable)
--- a/yosys-sim-script
+++ b/yosys-sim-script
@@ -1,3 +1,3 @@
-read_verilog -sv flash.v
+read_verilog -sv -DSIM flash.v
 prep -top top -nordff
-sim -clock CLK -vcd test.vcd -n 1000
+sim -clock CLK -vcd test.vcd -n 3000