Slightly simpler writer, P becomes freeptr

[clump.git] / writer.v

diff --git a/writer.v b/writer.v
index 37f6e0a3fba1da519db22d74cf78830c69aa9eac..c53d89f21c0ccf6487f6c8d87e17ed4f8d014dc1 100644 (file)
--- a/writer.v
+++ b/writer.v
@@ -3,39 +3,36 @@
 `define STATE_WRITE2       2'b10
 `define STATE_INCREMENT    2'b11
 
-module WRITER (input clk, input clk_enable, output reg [7:0] uart_tx_byte, output reg uart_tx_signal = 0, input uart_is_transmitting, output reg finished = 0, output [12:0] ram_addr, input [15:0] ram_do, input [12:0] P);
+module WRITER (input clk, input clk_enable, output reg [7:0] tx_byte, output reg tx_signal = 0, input tx_busy, output reg finished = 0, output [12:0] ram_addr, input [15:0] ram_do, input [12:0] freeptr);
    reg [1:0] state = `STATE_START;
 
    reg [12:0] current_index;
-   reg [12:0] freeptr;
 
    assign ram_addr = current_index;
 
-   always @ (posedge clk)
+   always @ (posedge clk) begin
         if (clk_enable) begin
-               if(uart_tx_signal)
-                 uart_tx_signal <= 0;
+               if(tx_signal)
+                 tx_signal <= 0;
 
                case(state)
                  `STATE_START: begin
-                        finished <= 0;
                         current_index <= 4;
-                        freeptr <= P;
                         state <= `STATE_WRITE1;
                  end
 
                  `STATE_WRITE1: begin
-                        if(!uart_is_transmitting && !uart_tx_signal) begin
-                               uart_tx_signal <= 1;
-                               uart_tx_byte <= ram_do[15:8];
+                        if(!tx_busy && !tx_signal) begin
+                               tx_signal <= 1;
+                               tx_byte <= ram_do[15:8];
                                state <= `STATE_WRITE2;
                         end
                  end
 
                  `STATE_WRITE2: begin
-                        if(!uart_is_transmitting && !uart_tx_signal) begin
-                               uart_tx_signal <= 1;
-                               uart_tx_byte <= ram_do[7:0];
+                        if(!tx_busy && !tx_signal) begin
+                               tx_signal <= 1;
+                               tx_byte <= ram_do[7:0];
                                state <= `STATE_INCREMENT;
                         end
                  end
@@ -50,5 +47,8 @@ module WRITER (input clk, input clk_enable, output reg [7:0] uart_tx_byte, outpu
                         end
                  end
                endcase // case (state)
-        end
+        end // if (clk_enable)
+        else
+          finished <= 0;
+   end
 endmodule