all: $(PROJ).rpt $(PROJ).bin
%.blif: %.v
- yosys -p 'synth_ice40 -top top -blif $@' $<
+ tools/yosys/yosys -p 'synth_ice40 -top top -blif $@' $<
%.asc: $(PIN_DEF) %.blif
- arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^ -P tq144
+ tools/arachne-pnr/bin/arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^ -P tq144
%.bin: %.asc
- icepack $< $@
+ tools/icestorm/icepack/icepack $< $@
%.rpt: %.asc
- icetime -d $(DEVICE) -mtr $@ $<
+ tools/icestorm/icetime/icetime -d $(DEVICE) -mtr $@ $<
prog: $(PROJ).bin
- iceprog $<
+ tools/icestorm/iceprog/iceprog $<
clean:
rm -f $(PROJ).blif $(PROJ).asc $(PROJ).bin
--- /dev/null
+module EVAL(input clk, input mclk, input [7:0] Ein, output [7:0] Eout, output [3:0] gcop, output [5:0] ostate, input conn_ea, input conn_et);
+ reg [21:0] rom_output;
+ reg [5:0] eostate = 6'o0;
+ reg [5:0] enstate;
+ reg [7:0] Ein_latched;
+
+ always @(posedge clk) begin
+ Ein_latched <= Ein;
+ end
+
+ wire et_lit = rom_output[21];
+ wire ea_lit = rom_output[20];
+ wire eaz_etz_eqv_disp = rom_output[19];
+ wire et_disp = rom_output[18];
+ wire rdC = rom_output[17];
+ wire rdL = rom_output[16];
+ wire rdN = rom_output[15];
+ wire rdXp = rom_output[14];
+ wire rdX = rom_output[13];
+ wire rdV = rom_output[12];
+ wire ldC = rom_output[11];
+ wire ldL = rom_output[10];
+ wire ldN = rom_output[9];
+ wire ldX = rom_output[8];
+ wire ldV = rom_output[7];
+ wire [3:0] gcop = rom_output[6:3];
+ wire [2:0] lit = rom_output[2:0];
+
+ always @* begin
+ case(eostate)
+ 6'o00: begin rom_output <= 22'o14004002; enstate <= 6'o01; end
+ 6'o01: begin rom_output <= 22'o14001000; enstate <= 6'o33; end
+ 6'o02: begin rom_output <= 22'o02040200; enstate <= 6'o23; end
+ 6'o03: begin rom_output <= 22'o00400120; enstate <= 6'o20; end
+ 6'o04: begin rom_output <= 22'o00010110; enstate <= 6'o64; end
+ 6'o05: begin rom_output <= 22'o00001170; enstate <= 6'o22; end
+ 6'o06: begin rom_output <= 22'o14000013; enstate <= 6'o71; end
+ 6'o07: begin rom_output <= 22'o00000000; enstate <= 6'o07; end
+ 6'o10: begin rom_output <= 22'o00020200; enstate <= 6'o45; end
+ 6'o11: begin rom_output <= 22'o00020200; enstate <= 6'o45; end
+ 6'o12: begin rom_output <= 22'o00100140; enstate <= 6'o02; end
+ 6'o13: begin rom_output <= 22'o00020200; enstate <= 6'o45; end
+ 6'o14: begin rom_output <= 22'o00020010; enstate <= 6'o53; end
+ 6'o15: begin rom_output <= 22'o00020010; enstate <= 6'o03; end
+ 6'o16: begin rom_output <= 22'o14002000; enstate <= 6'o40; end
+ 6'o17: begin rom_output <= 22'o00020010; enstate <= 6'o30; end
+ 6'o20: begin rom_output <= 22'o00100110; enstate <= 6'o21; end
+ 6'o21: begin rom_output <= 22'o10004161; enstate <= 6'o61; end
+ 6'o22: begin rom_output <= 22'o00004030; enstate <= 6'o24; end
+ 6'o23: begin rom_output <= 22'o00010500; enstate <= 6'o02; end
+ 6'o24: begin rom_output <= 22'o02010070; enstate <= 6'o33; end
+ 6'o25: begin rom_output <= 22'o00000040; enstate <= 6'o26; end
+ 6'o26: begin rom_output <= 22'o00010120; enstate <= 6'o30; end
+ 6'o27: begin rom_output <= 22'o00000240; enstate <= 6'o45; end
+ 6'o30: begin rom_output <= 22'o00000350; enstate <= 6'o45; end
+ 6'o31: begin rom_output <= 22'o00001150; enstate <= 6'o32; end
+ 6'o32: begin rom_output <= 22'o02200010; enstate <= 6'o63; end
+ 6'o33: begin rom_output <= 22'o01000440; enstate <= 6'o10; end
+ 6'o34: begin rom_output <= 22'o00201000; enstate <= 6'o35; end
+ 6'o35: begin rom_output <= 22'o00010020; enstate <= 6'o62; end
+ 6'o36: begin rom_output <= 22'o00400120; enstate <= 6'o54; end
+ 6'o37: begin rom_output <= 22'o01000430; enstate <= 6'o10; end
+ 6'o40: begin rom_output <= 22'o00020010; enstate <= 6'o36; end
+ 6'o41: begin rom_output <= 22'o00010020; enstate <= 6'o30; end
+ 6'o42: begin rom_output <= 22'o00010010; enstate <= 6'o30; end
+ 6'o43: begin rom_output <= 22'o00200010; enstate <= 6'o25; end
+ 6'o44: begin rom_output <= 22'o02010000; enstate <= 6'o55; end
+ 6'o45: begin rom_output <= 22'o01400020; enstate <= 6'o04; end
+ 6'o46: begin rom_output <= 22'o00200200; enstate <= 6'o45; end
+ 6'o47: begin rom_output <= 22'o00010010; enstate <= 6'o31; end
+ 6'o50: begin rom_output <= 22'o00000060; enstate <= 6'o51; end
+ 6'o51: begin rom_output <= 22'o00004030; enstate <= 6'o52; end
+ 6'o52: begin rom_output <= 22'o01000450; enstate <= 6'o40; end
+ 6'o53: begin rom_output <= 22'o00100120; enstate <= 6'o70; end
+ 6'o54: begin rom_output <= 22'o00100110; enstate <= 6'o56; end
+ 6'o55: begin rom_output <= 22'o14000201; enstate <= 6'o45; end
+ 6'o56: begin rom_output <= 22'o00200110; enstate <= 6'o60; end
+ 6'o57: begin rom_output <= 22'o14000200; enstate <= 6'o45; end
+ 6'o60: begin rom_output <= 22'o10004160; enstate <= 6'o61; end
+ 6'o61: begin rom_output <= 22'o00020020; enstate <= 6'o62; end
+ 6'o62: begin rom_output <= 22'o01000550; enstate <= 6'o10; end
+ 6'o63: begin rom_output <= 22'o02000030; enstate <= 6'o63; end
+ 6'o64: begin rom_output <= 22'o00002150; enstate <= 6'o65; end
+ 6'o65: begin rom_output <= 22'o00400010; enstate <= 6'o66; end
+ 6'o66: begin rom_output <= 22'o00001040; enstate <= 6'o50; end
+ 6'o67: begin rom_output <= 22'o00100130; enstate <= 6'o34; end
+ 6'o70: begin rom_output <= 22'o10000363; enstate <= 6'o45; end
+ 6'o71: begin rom_output <= 22'o00010130; enstate <= 6'o07; end
+ default: begin rom_output <= 22'o00000000; enstate <= 6'o07; end
+ endcase
+ end // always @ *
+
+ always @ (posedge clk) begin
+ eostate <=
+ et_disp ? (enstate | E[7:5]) :
+ eaz_etz_eqv_disp ? (enstate | {ea_zero, et_zero, 1'b0}) :
+ enstate;
+ end
+
+ assign ostate = eostate;
+
+ reg [7:0] V;
+ reg [7:0] X;
+ reg [7:0] N;
+ reg [7:0] L;
+ reg [7:0] C;
+
+ wire [7:0] E;
+
+ wire [7:0] EfromV = rdV ? V : 0;
+ wire [7:0] EfromX = rdX ? X : 0;
+ wire [7:0] EfromXp = rdXp ? {X[7:5], X[4:0] + 1} : 0;
+ wire [7:0] EfromN = rdN ? N : 0;
+ wire [7:0] EfromL = rdL ? L : 0;
+ wire [7:0] EfromC = rdC ? C : 0;
+ wire [4:0] EAfromEin = conn_ea ? Ein[4:0] : 0;
+ wire [3:0] ETfromEin = conn_et ? Ein[7:5] : 0;
+ wire [7:0] EfromEin = {ETfromEin, EAfromEin};
+ wire [4:0] EAfromLIT = ea_lit ? {1'b0, lit, 1'b0} : 0;
+ wire [3:0] ETfromLIT = et_lit ? lit : 0;
+ wire [7:0] EfromLIT = {ETfromLIT, EAfromLIT};
+
+ assign E = EfromV | EfromX | EfromXp | EfromN | EfromL | EfromC | EfromLIT | EfromEin;
+ assign Eout = EfromV | EfromX | EfromXp | EfromN | EfromL | EfromC | EfromLIT;
+
+ always @ (posedge clk) begin
+ if (ldV) V <= E;
+ if (ldX) X <= E;
+ if (ldN) N <= E;
+ if (ldL) L <= E;
+ if (ldC) C <= E;
+ end
+endmodule // EVAL
-`include "processor_4.v"
+`include "lisp_processor.v"
module top (input CLK, output [4:0] LED, output UART_TX, input UART_RX);
// Prescaler on the clock
end
// Connect up the processor
- PROCESSOR cpu(.clk(counter[10]),
+ PROCESSOR cpu(.clk(counter[7]),
.led(LED),
.uart_tx(UART_TX),
.uart_rx(UART_RX));
-module GC (input clk, input mclk, input [7:0] Ein, output [7:0] Eout, input [3:0] gcop, output [5:0] ostate, output step_eval);
- reg [5:0] gostate = 6'o2;
- reg [5:0] gnstate;
+`include "gcram.v"
+
+module GC (input clk, input mclk, input [7:0] Ein, output [7:0] Eout, input [3:0] gcop, output [5:0] ostate, output conn_et, output conn_ea, output step_eval, output [7:0] result);
reg [15:0] rom_output;
- reg [7:0] Ein_latched;
+ reg [5:0] gostate = 6'o0;
+ reg [5:0] gnstate;
+ reg [7:0] Ein_latched = 6'h44; // initial value of E
always @(posedge clk) begin
Ein_latched <= Ein;
wire ldQ = rom_output[5];
wire ldP = rom_output[4];
wire conn_i = rom_output[3];
- wire conn_et = rom_output[2];
- wire conn_ea = rom_output[1];
+ assign conn_et = rom_output[2];
+ assign conn_ea = rom_output[1];
assign step_eval = rom_output[0];
wire ga_zero = ~|G[7:5];
6'o07: begin rom_output <= 16'o002020; gnstate <= 6'o10; end
6'o10: begin rom_output <= 16'o001200; gnstate <= 6'o11; end
6'o11: begin rom_output <= 16'o004020; gnstate <= 6'o12; end
- 6'o12: begin rom_output <= 16'o002100; gnstate <= 6'o13; end
+ 6'o12: begin rom_output <= 16'o002100 | (1 << 12); gnstate <= 6'o13; end
6'o13: begin rom_output <= 16'o000057; gnstate <= 6'o02; end
6'o14: begin rom_output <= 16'o004020; gnstate <= 6'o04; end
6'o15: begin rom_output <= 16'o000246; gnstate <= 6'o16; end
6'o57: begin rom_output <= 16'o004007; gnstate <= 6'o02; end
default: begin rom_output <= 16'o040000; gnstate <= 6'o20; end
endcase; // case (gostate)
- end // always @ (posedge mclk)
+ end // always @ *
always @ (posedge clk) begin
gostate <=
- /* ga_zero_disp ? (gnstate | ga_zero) : */
+ ga_zero_disp ? (gnstate | ga_zero) :
gcop_disp ? (gnstate | gcop) :
gnstate;
end // always @ (posedge clk)
assign ostate = gostate;
- reg [4:0] P = 5'b0; // free storage pointer begins at 0
+ reg [4:0] P;
reg [7:0] Q;
reg [7:0] R;
reg [7:0] S;
wire [7:0] I;
wire [7:0] G;
+ wire [7:0] Gout;
/*
assign G = rdR ? R : 8'bzzzzzzzz;
wire [7:0] GfromE = {GTfromE, GAfromE};
assign G = GfromR | GfromQ | GfromP | GfromP_plus | GfromI | GfromE;
+ assign Gout = GfromR | GfromQ | GfromP | GfromP_plus | GfromI;
+
+ assign Eout[4:0] = conn_ea ? Gout[4:0] : 0;
+ assign Eout[7:5] = conn_et ? Gout[7:5] : 0;
- assign Eout[4:0] = conn_ea ? G[4:0] : 0;
- assign Eout[7:5] = conn_et ? G[7:5] : 0;
-
- generic_dpram #(.aw(5), .dw(8)) RAM
- ( .rclk(mclk),
- .wclk(mclk),
- .rrst(1'b0),
- .wrst(1'b0),
- .rce(1'b1),
- .wce(1'b1),
-
- .oe(1'b1),
- .we(write),
- .raddr(A),
- .waddr(A),
- .do(I),
- .di(S));
+ GCRAM gcram (.clk(mclk), .we(write), .addr(A), .do(I), .di(S), .result(result));
always @ (posedge clk) begin
if (ldS) S = G;
--- /dev/null
+module GCRAM
+(input clk, input we, input[5:0] addr, input[7:0] di, output reg [7:0] do, output reg [7:0] result);
+ reg [7:0] mem [(1<<5)-1:0];
+
+ always @ (posedge clk)
+ do <= #1 mem[addr];
+
+ always @ (posedge clk)
+ if (we)
+ mem[addr] <= #1 di;
+
+ always @ (posedge clk)
+ result <= mem[6];
+
+ initial begin
+ mem[0] <= 0;
+ mem[1] <= 0;
+ mem[2] <= 8'b00100000;
+ mem[3] <= 8'b00100000;
+ mem[4] <= 8'd8;
+ mem[5] <= 8'b11101000; /* QUOTE 8 */
+ mem[6] <= 0;
+ mem[7] <= 8'd49;
+ mem[8] <= 8'd49;
+ mem[9] <= 8'd49;
+ end
+endmodule
--- /dev/null
+`include "asciihex.v"
+`include "generic_fifo_sc_a.v"
+`include "gc.v"
+`include "eval.v"
+`include "ram.v"
+`include "rom.v"
+`include "prescaler.v"
+`include "single_trigger.v"
+`include "uart.v"
+
+`define GCOP_NOP 4'd0
+`define GCOP_CDR 4'd1
+`define GCOP_CAR 4'd2
+`define GCOP_CDRQ 4'd3
+`define GCOP_CARQ 4'd4
+`define GCOP_CARR 4'd5
+`define GCOP_CDRRX 4'd6
+`define GCOP_CARRX 4'd7
+`define GCOP_CDRQX 4'd8
+`define GCOP_CONS 4'd9
+`define GCOP_XCONS 4'd10
+`define GCOP_RPLACDR 4'd11
+`define GCOP_LDQ 4'd12
+`define GCOP_RDQ 4'd13
+`define GCOP_RDQA 4'd14
+`define GCOP_RDQCDRRX 4'd15
+
+module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx);
+ wire [7:0] result;
+
+ reg [1:0] counter = 0;
+
+ reg gc_clock = counter[1];
+ wire eval_clock = !counter[1] & step_eval;
+
+ always @ (posedge clk)
+ counter <= counter + 1;
+
+ wire [7:0] E1;
+ wire [7:0] E2;
+ wire [3:0] gcop;
+ wire [5:0] gostate;
+ wire [5:0] eostate;
+ wire conn_ea;
+ wire conn_et;
+
+ wire step_eval;
+
+ GC gc (.clk(gc_clock), .mclk(clk), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .result(result));
+
+ EVAL eval (.clk(eval_clock), .mclk(clk), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et));
+
+ // UART outputs
+ wire uart_rx_signal;
+ wire [7:0] uart_rx_byte;
+ wire uart_is_receiving;
+ wire uart_is_transmitting;
+ wire uart_rx_error;
+
+ // Input logic
+ wire [3:0] fifo_in;
+ wire [3:0] fifo_out;
+ wire fifo_full;
+ wire fifo_empty;
+ wire fifo_re = 0;//eval_clock & inst == `INST_READ & !fifo_empty;
+ wire fifo_we = uart_rx_signal & !fifo_full;
+
+ ascii_to_hex a2h (.ascii({1'b0, uart_rx_byte[6:0]}), .hex(fifo_in));
+
+ generic_fifo_sc_a #(.dw(4), .aw(4)) fifo
+ (.clk(clk),
+ .rst(1'b1),
+ .re(fifo_re),
+ .we(fifo_we),
+ .din(fifo_in),
+ .dout(fifo_out),
+ .full(fifo_full),
+ .empty(fifo_empty));
+
+ // UART logic
+ reg uart_tx_signal = 1;
+ wire [7:0] uart_tx_byte = result;
+
+ // 300 baud uart
+ uart #(.CLOCK_DIVIDE(39)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error));
+
+ // Assign the outputs
+ assign led[0] = eval_clock;
+ assign led[1] = uart_is_transmitting;
+ assign led[2] = uart_is_receiving;
+ assign led[3] = recv_error;
+endmodule
projects / clump.git / commitdiff