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2ed306f8 MG |
1 | `include "gcram.v" |
2 | ||
3 | module GC (input clk, input mclk, input [7:0] Ein, output [7:0] Eout, input [3:0] gcop, output [5:0] ostate, output conn_et, output conn_ea, output step_eval, output [7:0] result); | |
9e30ab0c | 4 | reg [15:0] rom_output; |
2ed306f8 MG |
5 | reg [5:0] gostate = 6'o0; |
6 | reg [5:0] gnstate; | |
7 | reg [7:0] Ein_latched = 6'h44; // initial value of E | |
a051754e MG |
8 | |
9 | always @(posedge clk) begin | |
10 | Ein_latched <= Ein; | |
11 | end | |
12 | ||
13 | wire ga_zero_disp = rom_output[15]; | |
14 | wire gcop_disp = rom_output[14]; | |
15 | wire write = rom_output[13]; | |
16 | wire adr = rom_output[12]; | |
17 | wire rdR = rom_output[11]; | |
18 | wire rdQ = rom_output[10]; | |
19 | wire rdP_plus = rom_output[9]; | |
20 | wire rdP = rom_output[8]; | |
21 | wire ldS = rom_output[7]; | |
22 | wire ldR = rom_output[6]; | |
23 | wire ldQ = rom_output[5]; | |
24 | wire ldP = rom_output[4]; | |
25 | wire conn_i = rom_output[3]; | |
2ed306f8 MG |
26 | assign conn_et = rom_output[2]; |
27 | assign conn_ea = rom_output[1]; | |
a051754e MG |
28 | assign step_eval = rom_output[0]; |
29 | ||
30 | wire ga_zero = ~|G[7:5]; | |
31 | ||
32 | always @* begin | |
33 | case(gostate) | |
34 | 6'o00: begin rom_output <= 16'o010242; gnstate <= 6'o01; end | |
35 | 6'o01: begin rom_output <= 16'o000031; gnstate <= 6'o02; end | |
36 | 6'o02: begin rom_output <= 16'o040000; gnstate <= 6'o20; end | |
37 | 6'o03: begin rom_output <= 16'o000126; gnstate <= 6'o04; end | |
38 | 6'o04: begin rom_output <= 16'o001200; gnstate <= 6'o05; end | |
39 | 6'o05: begin rom_output <= 16'o002020; gnstate <= 6'o06; end | |
40 | 6'o06: begin rom_output <= 16'o000051; gnstate <= 6'o02; end | |
41 | 6'o07: begin rom_output <= 16'o002020; gnstate <= 6'o10; end | |
42 | 6'o10: begin rom_output <= 16'o001200; gnstate <= 6'o11; end | |
43 | 6'o11: begin rom_output <= 16'o004020; gnstate <= 6'o12; end | |
2ed306f8 | 44 | 6'o12: begin rom_output <= 16'o002100 | (1 << 12); gnstate <= 6'o13; end |
a051754e MG |
45 | 6'o13: begin rom_output <= 16'o000057; gnstate <= 6'o02; end |
46 | 6'o14: begin rom_output <= 16'o004020; gnstate <= 6'o04; end | |
47 | 6'o15: begin rom_output <= 16'o000246; gnstate <= 6'o16; end | |
48 | 6'o16: begin rom_output <= 16'o020001; gnstate <= 6'o02; end | |
49 | 6'o17: begin rom_output <= 16'o002100; gnstate <= 6'o42; end | |
50 | 6'o20: begin rom_output <= 16'o000001; gnstate <= 6'o02; end | |
51 | 6'o21: begin rom_output <= 16'o010306; gnstate <= 6'o06; end | |
52 | 6'o22: begin rom_output <= 16'o000440; gnstate <= 6'o03; end | |
53 | 6'o23: begin rom_output <= 16'o012200; gnstate <= 6'o12; end | |
54 | 6'o24: begin rom_output <= 16'o000500; gnstate <= 6'o07; end | |
55 | 6'o25: begin rom_output <= 16'o004040; gnstate <= 6'o24; end | |
56 | 6'o26: begin rom_output <= 16'o014200; gnstate <= 6'o06; end | |
57 | 6'o27: begin rom_output <= 16'o000440; gnstate <= 6'o14; end | |
58 | 6'o30: begin rom_output <= 16'o012300; gnstate <= 6'o06; end | |
59 | 6'o31: begin rom_output <= 16'o111300; gnstate <= 6'o44; end | |
60 | 6'o32: begin rom_output <= 16'o111300; gnstate <= 6'o40; end | |
61 | 6'o33: begin rom_output <= 16'o014200; gnstate <= 6'o15; end | |
62 | 6'o34: begin rom_output <= 16'o000047; gnstate <= 6'o02; end | |
63 | 6'o35: begin rom_output <= 16'o002007; gnstate <= 6'o02; end | |
64 | 6'o36: begin rom_output <= 16'o002003; gnstate <= 6'o02; end | |
65 | 6'o37: begin rom_output <= 16'o014200; gnstate <= 6'o55; end | |
66 | 6'o40: begin rom_output <= 16'o004020; gnstate <= 6'o17; end | |
67 | 6'o41: begin rom_output <= 16'o000000; gnstate <= 6'o41; end | |
68 | 6'o42: begin rom_output <= 16'o000206; gnstate <= 6'o47; end | |
69 | 6'o43: begin rom_output <= 16'o000106; gnstate <= 6'o46; end | |
70 | 6'o44: begin rom_output <= 16'o004020; gnstate <= 6'o43; end | |
71 | 6'o45: begin rom_output <= 16'o000000; gnstate <= 6'o41; end | |
72 | 6'o46: begin rom_output <= 16'o002200; gnstate <= 6'o47; end | |
73 | 6'o47: begin rom_output <= 16'o020440; gnstate <= 6'o50; end | |
74 | 6'o50: begin rom_output <= 16'o111200; gnstate <= 6'o52; end | |
75 | 6'o51: begin rom_output <= 16'o021100; gnstate <= 6'o54; end | |
76 | 6'o52: begin rom_output <= 16'o004200; gnstate <= 6'o51; end | |
77 | 6'o53: begin rom_output <= 16'o000000; gnstate <= 6'o41; end | |
78 | 6'o54: begin rom_output <= 16'o004021; gnstate <= 6'o02; end | |
79 | 6'o55: begin rom_output <= 16'o002100; gnstate <= 6'o56; end | |
80 | 6'o56: begin rom_output <= 16'o000050; gnstate <= 6'o57; end | |
81 | 6'o57: begin rom_output <= 16'o004007; gnstate <= 6'o02; end | |
82 | default: begin rom_output <= 16'o040000; gnstate <= 6'o20; end | |
83 | endcase; // case (gostate) | |
2ed306f8 | 84 | end // always @ * |
a051754e MG |
85 | |
86 | always @ (posedge clk) begin | |
87 | gostate <= | |
2ed306f8 | 88 | ga_zero_disp ? (gnstate | ga_zero) : |
a051754e MG |
89 | gcop_disp ? (gnstate | gcop) : |
90 | gnstate; | |
91 | end // always @ (posedge clk) | |
92 | ||
93 | assign ostate = gostate; | |
94 | ||
2ed306f8 | 95 | reg [4:0] P; |
a051754e MG |
96 | reg [7:0] Q; |
97 | reg [7:0] R; | |
98 | reg [7:0] S; | |
99 | ||
100 | reg [4:0] A; // latched address | |
101 | ||
102 | wire [7:0] I; | |
103 | ||
104 | wire [7:0] G; | |
2ed306f8 | 105 | wire [7:0] Gout; |
a051754e MG |
106 | |
107 | /* | |
108 | assign G = rdR ? R : 8'bzzzzzzzz; | |
109 | assign G = rdQ ? Q : 8'bzzzzzzzz; | |
110 | assign G = rdP ? {3'b0, P} : 8'bzzzzzzzz; | |
111 | assign G = rdP_plus ? {3'b0, P+1} : 8'bzzzzzzzz; | |
112 | assign G = conn_i ? I : 8'bzzzzzzzz; | |
113 | assign G[4:0] = conn_ea ? E[4:0] : 5'bzzzzz; | |
114 | assign G[7:5] = conn_et ? E[7:5] : 3'bzzz; | |
115 | ||
116 | assign E[4:0] = conn_ea ? G[4:0] : 5'bzzzzz; | |
117 | assign E[7:5] = conn_et ? G[7:5] : 3'bzzz; | |
118 | */ | |
119 | ||
120 | wire [7:0] GfromR = rdR ? R : 0; | |
121 | wire [7:0] GfromQ = rdQ ? Q : 0; | |
122 | wire [7:0] GfromP = rdP ? {3'b0, P} : 0; | |
123 | wire [7:0] GfromP_plus = rdP_plus ? {3'b0, P + 1} : 0; | |
124 | wire [7:0] GfromI = conn_i ? I : 0; | |
125 | wire [4:0] GAfromE = conn_ea ? Ein_latched[4:0] : 0; | |
126 | wire [3:0] GTfromE = conn_et ? Ein_latched[7:5] : 0; | |
127 | wire [7:0] GfromE = {GTfromE, GAfromE}; | |
128 | ||
129 | assign G = GfromR | GfromQ | GfromP | GfromP_plus | GfromI | GfromE; | |
2ed306f8 MG |
130 | assign Gout = GfromR | GfromQ | GfromP | GfromP_plus | GfromI; |
131 | ||
132 | assign Eout[4:0] = conn_ea ? Gout[4:0] : 0; | |
133 | assign Eout[7:5] = conn_et ? Gout[7:5] : 0; | |
a051754e | 134 | |
2ed306f8 | 135 | GCRAM gcram (.clk(mclk), .we(write), .addr(A), .do(I), .di(S), .result(result)); |
a051754e MG |
136 | |
137 | always @ (posedge clk) begin | |
138 | if (ldS) S = G; | |
139 | if (ldP) P <= G[4:0]; | |
140 | if (ldR) R <= G; | |
141 | if (ldQ) Q <= G; | |
142 | if (adr) A <= S[4:0]; | |
143 | end | |
144 | endmodule // GC |