Commit | Line | Data |
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a051754e MG |
1 | module GC (input clk, input mclk, input [7:0] Ein, output [7:0] Eout, input [3:0] gcop, output [5:0] ostate, output step_eval); |
2 | reg [5:0] gostate = 6'o2; | |
3 | reg [5:0] gnstate; | |
4 | reg [16:0] rom_output; | |
5 | reg [7:0] Ein_latched; | |
6 | ||
7 | always @(posedge clk) begin | |
8 | Ein_latched <= Ein; | |
9 | end | |
10 | ||
11 | wire ga_zero_disp = rom_output[15]; | |
12 | wire gcop_disp = rom_output[14]; | |
13 | wire write = rom_output[13]; | |
14 | wire adr = rom_output[12]; | |
15 | wire rdR = rom_output[11]; | |
16 | wire rdQ = rom_output[10]; | |
17 | wire rdP_plus = rom_output[9]; | |
18 | wire rdP = rom_output[8]; | |
19 | wire ldS = rom_output[7]; | |
20 | wire ldR = rom_output[6]; | |
21 | wire ldQ = rom_output[5]; | |
22 | wire ldP = rom_output[4]; | |
23 | wire conn_i = rom_output[3]; | |
24 | wire conn_et = rom_output[2]; | |
25 | wire conn_ea = rom_output[1]; | |
26 | assign step_eval = rom_output[0]; | |
27 | ||
28 | wire ga_zero = ~|G[7:5]; | |
29 | ||
30 | always @* begin | |
31 | case(gostate) | |
32 | 6'o00: begin rom_output <= 16'o010242; gnstate <= 6'o01; end | |
33 | 6'o01: begin rom_output <= 16'o000031; gnstate <= 6'o02; end | |
34 | 6'o02: begin rom_output <= 16'o040000; gnstate <= 6'o20; end | |
35 | 6'o03: begin rom_output <= 16'o000126; gnstate <= 6'o04; end | |
36 | 6'o04: begin rom_output <= 16'o001200; gnstate <= 6'o05; end | |
37 | 6'o05: begin rom_output <= 16'o002020; gnstate <= 6'o06; end | |
38 | 6'o06: begin rom_output <= 16'o000051; gnstate <= 6'o02; end | |
39 | 6'o07: begin rom_output <= 16'o002020; gnstate <= 6'o10; end | |
40 | 6'o10: begin rom_output <= 16'o001200; gnstate <= 6'o11; end | |
41 | 6'o11: begin rom_output <= 16'o004020; gnstate <= 6'o12; end | |
42 | 6'o12: begin rom_output <= 16'o002100; gnstate <= 6'o13; end | |
43 | 6'o13: begin rom_output <= 16'o000057; gnstate <= 6'o02; end | |
44 | 6'o14: begin rom_output <= 16'o004020; gnstate <= 6'o04; end | |
45 | 6'o15: begin rom_output <= 16'o000246; gnstate <= 6'o16; end | |
46 | 6'o16: begin rom_output <= 16'o020001; gnstate <= 6'o02; end | |
47 | 6'o17: begin rom_output <= 16'o002100; gnstate <= 6'o42; end | |
48 | 6'o20: begin rom_output <= 16'o000001; gnstate <= 6'o02; end | |
49 | 6'o21: begin rom_output <= 16'o010306; gnstate <= 6'o06; end | |
50 | 6'o22: begin rom_output <= 16'o000440; gnstate <= 6'o03; end | |
51 | 6'o23: begin rom_output <= 16'o012200; gnstate <= 6'o12; end | |
52 | 6'o24: begin rom_output <= 16'o000500; gnstate <= 6'o07; end | |
53 | 6'o25: begin rom_output <= 16'o004040; gnstate <= 6'o24; end | |
54 | 6'o26: begin rom_output <= 16'o014200; gnstate <= 6'o06; end | |
55 | 6'o27: begin rom_output <= 16'o000440; gnstate <= 6'o14; end | |
56 | 6'o30: begin rom_output <= 16'o012300; gnstate <= 6'o06; end | |
57 | 6'o31: begin rom_output <= 16'o111300; gnstate <= 6'o44; end | |
58 | 6'o32: begin rom_output <= 16'o111300; gnstate <= 6'o40; end | |
59 | 6'o33: begin rom_output <= 16'o014200; gnstate <= 6'o15; end | |
60 | 6'o34: begin rom_output <= 16'o000047; gnstate <= 6'o02; end | |
61 | 6'o35: begin rom_output <= 16'o002007; gnstate <= 6'o02; end | |
62 | 6'o36: begin rom_output <= 16'o002003; gnstate <= 6'o02; end | |
63 | 6'o37: begin rom_output <= 16'o014200; gnstate <= 6'o55; end | |
64 | 6'o40: begin rom_output <= 16'o004020; gnstate <= 6'o17; end | |
65 | 6'o41: begin rom_output <= 16'o000000; gnstate <= 6'o41; end | |
66 | 6'o42: begin rom_output <= 16'o000206; gnstate <= 6'o47; end | |
67 | 6'o43: begin rom_output <= 16'o000106; gnstate <= 6'o46; end | |
68 | 6'o44: begin rom_output <= 16'o004020; gnstate <= 6'o43; end | |
69 | 6'o45: begin rom_output <= 16'o000000; gnstate <= 6'o41; end | |
70 | 6'o46: begin rom_output <= 16'o002200; gnstate <= 6'o47; end | |
71 | 6'o47: begin rom_output <= 16'o020440; gnstate <= 6'o50; end | |
72 | 6'o50: begin rom_output <= 16'o111200; gnstate <= 6'o52; end | |
73 | 6'o51: begin rom_output <= 16'o021100; gnstate <= 6'o54; end | |
74 | 6'o52: begin rom_output <= 16'o004200; gnstate <= 6'o51; end | |
75 | 6'o53: begin rom_output <= 16'o000000; gnstate <= 6'o41; end | |
76 | 6'o54: begin rom_output <= 16'o004021; gnstate <= 6'o02; end | |
77 | 6'o55: begin rom_output <= 16'o002100; gnstate <= 6'o56; end | |
78 | 6'o56: begin rom_output <= 16'o000050; gnstate <= 6'o57; end | |
79 | 6'o57: begin rom_output <= 16'o004007; gnstate <= 6'o02; end | |
80 | default: begin rom_output <= 16'o040000; gnstate <= 6'o20; end | |
81 | endcase; // case (gostate) | |
82 | end // always @ (posedge mclk) | |
83 | ||
84 | always @ (posedge clk) begin | |
85 | gostate <= | |
86 | /* ga_zero_disp ? (gnstate | ga_zero) : */ | |
87 | gcop_disp ? (gnstate | gcop) : | |
88 | gnstate; | |
89 | end // always @ (posedge clk) | |
90 | ||
91 | assign ostate = gostate; | |
92 | ||
93 | reg [4:0] P = 5'b0; // free storage pointer begins at 0 | |
94 | reg [7:0] Q; | |
95 | reg [7:0] R; | |
96 | reg [7:0] S; | |
97 | ||
98 | reg [4:0] A; // latched address | |
99 | ||
100 | wire [7:0] I; | |
101 | ||
102 | wire [7:0] G; | |
103 | ||
104 | /* | |
105 | assign G = rdR ? R : 8'bzzzzzzzz; | |
106 | assign G = rdQ ? Q : 8'bzzzzzzzz; | |
107 | assign G = rdP ? {3'b0, P} : 8'bzzzzzzzz; | |
108 | assign G = rdP_plus ? {3'b0, P+1} : 8'bzzzzzzzz; | |
109 | assign G = conn_i ? I : 8'bzzzzzzzz; | |
110 | assign G[4:0] = conn_ea ? E[4:0] : 5'bzzzzz; | |
111 | assign G[7:5] = conn_et ? E[7:5] : 3'bzzz; | |
112 | ||
113 | assign E[4:0] = conn_ea ? G[4:0] : 5'bzzzzz; | |
114 | assign E[7:5] = conn_et ? G[7:5] : 3'bzzz; | |
115 | */ | |
116 | ||
117 | wire [7:0] GfromR = rdR ? R : 0; | |
118 | wire [7:0] GfromQ = rdQ ? Q : 0; | |
119 | wire [7:0] GfromP = rdP ? {3'b0, P} : 0; | |
120 | wire [7:0] GfromP_plus = rdP_plus ? {3'b0, P + 1} : 0; | |
121 | wire [7:0] GfromI = conn_i ? I : 0; | |
122 | wire [4:0] GAfromE = conn_ea ? Ein_latched[4:0] : 0; | |
123 | wire [3:0] GTfromE = conn_et ? Ein_latched[7:5] : 0; | |
124 | wire [7:0] GfromE = {GTfromE, GAfromE}; | |
125 | ||
126 | assign G = GfromR | GfromQ | GfromP | GfromP_plus | GfromI | GfromE; | |
127 | ||
128 | assign Eout[4:0] = conn_ea ? G[4:0] : 0; | |
129 | assign Eout[7:5] = conn_et ? G[7:5] : 0; | |
130 | ||
131 | generic_dpram #(.aw(5), .dw(8)) RAM | |
132 | ( .rclk(mclk), | |
133 | .wclk(mclk), | |
134 | .rrst(1'b0), | |
135 | .wrst(1'b0), | |
136 | .rce(1'b1), | |
137 | .wce(1'b1), | |
138 | ||
139 | .oe(1'b1), | |
140 | .we(write), | |
141 | .raddr(A), | |
142 | .waddr(A), | |
143 | .do(I), | |
144 | .di(S)); | |
145 | ||
146 | always @ (posedge clk) begin | |
147 | if (ldS) S = G; | |
148 | if (ldP) P <= G[4:0]; | |
149 | if (ldR) R <= G; | |
150 | if (ldQ) Q <= G; | |
151 | if (adr) A <= S[4:0]; | |
152 | end | |
153 | endmodule // GC |