]> iEval git - clump.git/commitdiff
Initial commit
authorMarius Gavrilescu <marius@ieval.ro>
Mon, 4 Dec 2017 10:44:54 +0000 (12:44 +0200)
committerMarius Gavrilescu <marius@ieval.ro>
Mon, 4 Dec 2017 10:44:54 +0000 (12:44 +0200)
21 files changed:
.gitignore [new file with mode: 0644]
Makefile [new file with mode: 0644]
asciihex.v [new file with mode: 0644]
flash.pcf [new file with mode: 0644]
flash.txt [new file with mode: 0644]
flash.v [new file with mode: 0644]
gc.v [new file with mode: 0644]
generic_dpram.v [new file with mode: 0644]
generic_fifo_sc_a.v [new file with mode: 0644]
iCEburn.py [new file with mode: 0755]
libiceblink.py [new file with mode: 0644]
multiple_trigger.v [new file with mode: 0644]
prescaler.v [new file with mode: 0644]
processor_32.v [new file with mode: 0644]
processor_4.v [new file with mode: 0644]
ram.v [new file with mode: 0644]
rom.v [new file with mode: 0644]
single_trigger.v [new file with mode: 0644]
to-philippa.zip [new file with mode: 0644]
uart.v [new file with mode: 0644]
yosys-sim-script [new file with mode: 0755]

diff --git a/.gitignore b/.gitignore
new file mode 100644 (file)
index 0000000..5803134
--- /dev/null
@@ -0,0 +1,10 @@
+tools/
+to-phillippa.zip
+__pycache__
+\#*
+.#*
+test.vcd
+flash.blif
+flash.bin
+flash.asc
+flash.rpt
diff --git a/Makefile b/Makefile
new file mode 100644 (file)
index 0000000..f26533b
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,25 @@
+PROJ = flash
+PIN_DEF = flash.pcf
+DEVICE = hx1k
+
+all: $(PROJ).rpt $(PROJ).bin
+
+%.blif: %.v
+       yosys -p 'synth_ice40 -top top -blif $@' $<
+
+%.asc: $(PIN_DEF) %.blif
+       arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^ -P vq100
+
+%.bin: %.asc
+       icepack $< $@
+
+%.rpt: %.asc
+       icetime -d $(DEVICE) -mtr $@ $<
+
+prog: $(PROJ).bin
+       ./iCEburn.py  -e -v -w  $<
+
+clean:
+       rm -f $(PROJ).blif $(PROJ).asc $(PROJ).bin
+
+.PHONY: all prog clean
diff --git a/asciihex.v b/asciihex.v
new file mode 100644 (file)
index 0000000..cfd4487
--- /dev/null
@@ -0,0 +1,48 @@
+// convert ASCII 0-9A-Za-z to/from numbers
+
+module ascii_to_hex(input [7:0] ascii, output [3:0] hex);
+   wire [7:0] hex8;
+   assign hex8 =
+                          ascii > 8'd47 & ascii < 8'd58  ? ascii - 8'd48 :
+                          ascii > 8'd64 & ascii < 8'd71  ? ascii - 8'd55 :
+                          ascii > 8'd96 & ascii < 8'd103 ? ascii - 8'd87 : 8'bxxxx;
+   assign hex = hex8[3:0];
+
+/*   assign hex =
+                          ascii == 8'd48 ? 4'd0  :
+               ascii == 8'd49 ? 4'd1  :
+               ascii == 8'd50 ? 4'd2  :
+               ascii == 8'd51 ? 4'd3  :
+               ascii == 8'd52 ? 4'd4  :
+               ascii == 8'd53 ? 4'd5  :
+               ascii == 8'd54 ? 4'd6  :
+               ascii == 8'd55 ? 4'd7  :
+               ascii == 8'd56 ? 4'd8  :
+               ascii == 8'd57 ? 4'd9  :
+               ascii == 8'd65 ? 4'd10 :
+               ascii == 8'd66 ? 4'd11 :
+               ascii == 8'd67 ? 4'd12 :
+               ascii == 8'd68 ? 4'd13 :
+               ascii == 8'd69 ? 4'd14 : 4'd15;*/
+endmodule // ascii_to_hex
+
+module hex_to_ascii(input [3:0] hex, output [7:0] ascii);
+//   assign ascii = hex < 4'd10 ? 8'd48 + hex : 8'd55 + hex;
+   assign ascii =
+                                hex == 4'd0  ? 8'd48 :
+                                hex == 4'd1  ? 8'd49 :
+                                hex == 4'd2  ? 8'd50 :
+                                hex == 4'd3  ? 8'd51 :
+                                hex == 4'd4  ? 8'd52 :
+                                hex == 4'd5  ? 8'd53 :
+                                hex == 4'd6  ? 8'd54 :
+                                hex == 4'd7  ? 8'd55 :
+                                hex == 4'd8  ? 8'd56 :
+                                hex == 4'd9  ? 8'd57 :
+                                hex == 4'd10 ? 8'd65 :
+                                hex == 4'd11 ? 8'd66 :
+                                hex == 4'd12 ? 8'd67 :
+                                hex == 4'd13 ? 8'd68 :
+                                hex == 4'd14 ? 8'd69 :
+                                hex == 4'd15 ? 8'd70 : 8'bx;
+endmodule // hex_to_ascii
diff --git a/flash.pcf b/flash.pcf
new file mode 100644 (file)
index 0000000..7426699
--- /dev/null
+++ b/flash.pcf
@@ -0,0 +1,33 @@
+
+set_io OUT_R[0] 72
+set_io OUT_R[1] 69
+set_io OUT_R[2] 66
+
+set_io OUT_C[0] 87
+set_io OUT_C[1] 85
+set_io OUT_C[2] 82
+set_io OUT_C[3] 80
+set_io OUT_C[4] 78
+set_io OUT_C[5] 73
+set_io OUT_C[6] 71
+set_io OUT_C[7] 68
+
+set_io IND[0] 86
+set_io IND[1] 83
+set_io IND[2] 81
+set_io IND[3] 79
+
+set_io IN_R[0] 100
+set_io IN_R[1] 15
+set_io IN_R[2] 16
+set_io IN_R[3] 19
+
+set_io IN_C[0] 90
+set_io IN_C[1] 93
+set_io IN_C[2] 95
+set_io IN_C[3] 97
+
+set_io CLK 13
+
+set_io UART_TX 10
+set_io UART_RX 9
\ No newline at end of file
diff --git a/flash.txt b/flash.txt
new file mode 100644 (file)
index 0000000..9d1272a
--- /dev/null
+++ b/flash.txt
@@ -0,0 +1,4224 @@
+.comment arachne-pnr 0.1+154+0 (git sha1 6b83364, g++ 4.8.4-2ubuntu1~14.04.1 -O2)
+.device 1k
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diff --git a/flash.v b/flash.v
new file mode 100644 (file)
index 0000000..633cf6a
--- /dev/null
+++ b/flash.v
@@ -0,0 +1,96 @@
+`include "processor_4.v"
+
+module top (input CLK, output [7:0] OUT_C, output [2:0] OUT_R, output [3:0] IN_C, input [3:0] IN_R, output [3:0] IND, output UART_TX, input UART_RX);
+
+    wire [23:0] led;
+   
+    // Prescaler on the clock
+   
+    reg [24:0] counter = 0;
+
+    always @ (posedge CLK) begin
+      
+        counter <= counter + 1;
+   
+    end
+   
+    // Handle the inputs
+
+    reg [3:0] shift_in = 4'b1110;
+
+    always @ (negedge counter[13]) begin
+
+        shift_in <= { shift_in[2:0], shift_in[3] };
+      
+    end
+
+    assign IN_C = shift_in;
+
+    reg [15:0] buttons = 0;
+
+    always @ (posedge counter[13]) begin
+
+        case (shift_in)
+            4'b1110: begin
+                buttons[0] <= !IN_R[0];
+                buttons[4] <= !IN_R[1];
+                buttons[8] <= !IN_R[2];
+                buttons[12] <= !IN_R[3];    
+            end
+            4'b1101: begin
+                buttons[1] <= !IN_R[0];
+                buttons[5] <= !IN_R[1];
+                buttons[9] <= !IN_R[2];
+                buttons[13] <= !IN_R[3];      
+            end
+            4'b1011: begin
+                buttons[2] <= !IN_R[0];
+                buttons[6] <= !IN_R[1];
+                buttons[10] <= !IN_R[2];
+                buttons[14] <= !IN_R[3];
+            end
+            4'b0111: begin
+                buttons[3] <= !IN_R[0];
+                buttons[7] <= !IN_R[1];
+                buttons[11] <= !IN_R[2];
+                buttons[15] <= !IN_R[3];      
+            end
+        endcase
+
+    end
+
+    // Connect up the processor
+
+   PROCESSOR cpu(.clk(CLK),//counter[20]),
+                                .led(led),
+                                .indicators(IND),
+                                .uart_tx(UART_TX),
+                                .uart_rx(UART_RX),
+                                .buttons(buttons));
+
+    // Handle output stuff
+   
+    reg [7:0] out;
+
+    reg [2:0] shift_out = 3'b001;
+
+    always @ (posedge counter[7]) begin
+
+        if (shift_out[2] == 1)
+            out <= led[7:0];
+        if (shift_out[0] == 1)
+            out <= led[15:8];
+        if (shift_out[1] == 1)
+            out <= led[23:16];
+
+        shift_out <= { shift_out[1:0], shift_out[2] };
+
+   end
+
+   assign OUT_R = shift_out;
+   
+   assign OUT_C = out;
+
+endmodule 
+
+
diff --git a/gc.v b/gc.v
new file mode 100644 (file)
index 0000000..b840205
--- /dev/null
+++ b/gc.v
@@ -0,0 +1,153 @@
+module GC (input clk, input mclk, input [7:0] Ein, output [7:0] Eout, input [3:0] gcop, output [5:0] ostate, output step_eval);
+   reg [5:0] gostate = 6'o2;
+   reg [5:0] gnstate;
+   reg [16:0] rom_output;
+   reg [7:0]  Ein_latched;
+
+   always @(posedge clk) begin
+         Ein_latched <= Ein;
+   end
+
+   wire ga_zero_disp = rom_output[15];
+   wire gcop_disp    = rom_output[14];
+   wire write        = rom_output[13];
+   wire adr          = rom_output[12];
+   wire rdR          = rom_output[11];
+   wire rdQ          = rom_output[10];
+   wire rdP_plus     = rom_output[9];
+   wire rdP          = rom_output[8];
+   wire ldS          = rom_output[7];
+   wire ldR          = rom_output[6];
+   wire ldQ          = rom_output[5];
+   wire ldP          = rom_output[4];
+   wire conn_i       = rom_output[3];
+   wire conn_et      = rom_output[2];
+   wire conn_ea      = rom_output[1];
+   assign step_eval  = rom_output[0];
+
+   wire ga_zero = ~|G[7:5];
+
+   always @* begin
+         case(gostate)
+               6'o00:   begin rom_output <= 16'o010242; gnstate <= 6'o01; end
+               6'o01:   begin rom_output <= 16'o000031; gnstate <= 6'o02; end
+               6'o02:   begin rom_output <= 16'o040000; gnstate <= 6'o20; end
+               6'o03:   begin rom_output <= 16'o000126; gnstate <= 6'o04; end
+               6'o04:   begin rom_output <= 16'o001200; gnstate <= 6'o05; end
+               6'o05:   begin rom_output <= 16'o002020; gnstate <= 6'o06; end
+               6'o06:   begin rom_output <= 16'o000051; gnstate <= 6'o02; end
+               6'o07:   begin rom_output <= 16'o002020; gnstate <= 6'o10; end
+               6'o10:   begin rom_output <= 16'o001200; gnstate <= 6'o11; end
+               6'o11:   begin rom_output <= 16'o004020; gnstate <= 6'o12; end
+               6'o12:   begin rom_output <= 16'o002100; gnstate <= 6'o13; end
+               6'o13:   begin rom_output <= 16'o000057; gnstate <= 6'o02; end
+               6'o14:   begin rom_output <= 16'o004020; gnstate <= 6'o04; end
+               6'o15:   begin rom_output <= 16'o000246; gnstate <= 6'o16; end
+               6'o16:   begin rom_output <= 16'o020001; gnstate <= 6'o02; end
+               6'o17:   begin rom_output <= 16'o002100; gnstate <= 6'o42; end
+               6'o20:   begin rom_output <= 16'o000001; gnstate <= 6'o02; end
+               6'o21:   begin rom_output <= 16'o010306; gnstate <= 6'o06; end
+               6'o22:   begin rom_output <= 16'o000440; gnstate <= 6'o03; end
+               6'o23:   begin rom_output <= 16'o012200; gnstate <= 6'o12; end
+               6'o24:   begin rom_output <= 16'o000500; gnstate <= 6'o07; end
+               6'o25:   begin rom_output <= 16'o004040; gnstate <= 6'o24; end
+               6'o26:   begin rom_output <= 16'o014200; gnstate <= 6'o06; end
+               6'o27:   begin rom_output <= 16'o000440; gnstate <= 6'o14; end
+               6'o30:   begin rom_output <= 16'o012300; gnstate <= 6'o06; end
+               6'o31:   begin rom_output <= 16'o111300; gnstate <= 6'o44; end
+               6'o32:   begin rom_output <= 16'o111300; gnstate <= 6'o40; end
+               6'o33:   begin rom_output <= 16'o014200; gnstate <= 6'o15; end
+               6'o34:   begin rom_output <= 16'o000047; gnstate <= 6'o02; end
+               6'o35:   begin rom_output <= 16'o002007; gnstate <= 6'o02; end
+               6'o36:   begin rom_output <= 16'o002003; gnstate <= 6'o02; end
+               6'o37:   begin rom_output <= 16'o014200; gnstate <= 6'o55; end
+               6'o40:   begin rom_output <= 16'o004020; gnstate <= 6'o17; end
+               6'o41:   begin rom_output <= 16'o000000; gnstate <= 6'o41; end
+               6'o42:   begin rom_output <= 16'o000206; gnstate <= 6'o47; end
+               6'o43:   begin rom_output <= 16'o000106; gnstate <= 6'o46; end
+               6'o44:   begin rom_output <= 16'o004020; gnstate <= 6'o43; end
+               6'o45:   begin rom_output <= 16'o000000; gnstate <= 6'o41; end
+               6'o46:   begin rom_output <= 16'o002200; gnstate <= 6'o47; end
+               6'o47:   begin rom_output <= 16'o020440; gnstate <= 6'o50; end
+               6'o50:   begin rom_output <= 16'o111200; gnstate <= 6'o52; end
+               6'o51:   begin rom_output <= 16'o021100; gnstate <= 6'o54; end
+               6'o52:   begin rom_output <= 16'o004200; gnstate <= 6'o51; end
+               6'o53:   begin rom_output <= 16'o000000; gnstate <= 6'o41; end
+               6'o54:   begin rom_output <= 16'o004021; gnstate <= 6'o02; end
+               6'o55:   begin rom_output <= 16'o002100; gnstate <= 6'o56; end
+               6'o56:   begin rom_output <= 16'o000050; gnstate <= 6'o57; end
+               6'o57:   begin rom_output <= 16'o004007; gnstate <= 6'o02; end
+               default: begin rom_output <= 16'o040000; gnstate <= 6'o20; end
+         endcase; // case (gostate)
+   end // always @ (posedge mclk)
+
+   always @ (posedge clk) begin
+         gostate <=
+                          /*                           ga_zero_disp ? (gnstate | ga_zero) : */
+                               gcop_disp ? (gnstate | gcop) :
+                               gnstate;
+   end // always @ (posedge clk)
+
+   assign ostate = gostate;
+
+   reg [4:0] P = 5'b0; // free storage pointer begins at 0
+   reg [7:0] Q;
+   reg [7:0] R;
+   reg [7:0] S;
+
+   reg [4:0] A; // latched address
+
+   wire [7:0] I;
+
+   wire [7:0] G;
+
+   /*
+   assign G = rdR ? R : 8'bzzzzzzzz;
+   assign G = rdQ ? Q : 8'bzzzzzzzz;
+   assign G = rdP ? {3'b0, P} : 8'bzzzzzzzz;
+   assign G = rdP_plus ? {3'b0, P+1} : 8'bzzzzzzzz;
+   assign G = conn_i ? I : 8'bzzzzzzzz;
+   assign G[4:0] = conn_ea ? E[4:0] : 5'bzzzzz;
+   assign G[7:5] = conn_et ? E[7:5] : 3'bzzz;
+
+   assign E[4:0] = conn_ea ? G[4:0] : 5'bzzzzz;
+   assign E[7:5] = conn_et ? G[7:5] : 3'bzzz;
+       */
+
+   wire [7:0] GfromR = rdR ? R : 0;
+   wire [7:0] GfromQ = rdQ ? Q : 0;
+   wire [7:0] GfromP = rdP ? {3'b0, P} : 0;
+   wire [7:0] GfromP_plus = rdP_plus ? {3'b0, P + 1} : 0;
+   wire [7:0] GfromI = conn_i ? I : 0;
+   wire [4:0] GAfromE = conn_ea ? Ein_latched[4:0] : 0;
+   wire [3:0] GTfromE = conn_et ? Ein_latched[7:5] : 0;
+   wire [7:0] GfromE = {GTfromE, GAfromE};
+
+   assign G = GfromR | GfromQ | GfromP | GfromP_plus | GfromI | GfromE;
+
+   assign Eout[4:0] = conn_ea ? G[4:0] : 0;
+   assign Eout[7:5] = conn_et ? G[7:5] : 0;
+
+   generic_dpram #(.aw(5), .dw(8)) RAM
+        ( .rclk(mclk),
+          .wclk(mclk),
+          .rrst(1'b0),
+          .wrst(1'b0),
+          .rce(1'b1),
+          .wce(1'b1),
+
+          .oe(1'b1),
+          .we(write),
+          .raddr(A),
+          .waddr(A),
+          .do(I),
+          .di(S));
+
+   always @ (posedge clk) begin
+         if (ldS) S = G;
+         if (ldP) P <= G[4:0];
+         if (ldR) R <= G;
+         if (ldQ) Q <= G;
+         if (adr) A <= S[4:0];
+   end
+endmodule // GC
diff --git a/generic_dpram.v b/generic_dpram.v
new file mode 100644 (file)
index 0000000..ca0fced
--- /dev/null
@@ -0,0 +1,503 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  Generic Dual-Port Synchronous RAM                           ////
+////                                                              ////
+////  This file is part of memory library available from          ////
+////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
+////                                                              ////
+////  Description                                                 ////
+////  This block is a wrapper with common dual-port               ////
+////  synchronous memory interface for different                  ////
+////  types of ASIC and FPGA RAMs. Beside universal memory        ////
+////  interface it also provides behavioral model of generic      ////
+////  dual-port synchronous RAM.                                  ////
+////  It also contains a fully synthesizeable model for FPGAs.    ////
+////  It should be used in all OPENCORES designs that want to be  ////
+////  portable accross different target technologies and          ////
+////  independent of target memory.                               ////
+////                                                              ////
+////  Supported ASIC RAMs are:                                    ////
+////  - Artisan Dual-Port Sync RAM                                ////
+////  - Avant! Two-Port Sync RAM (*)                              ////
+////  - Virage 2-port Sync RAM                                    ////
+////                                                              ////
+////  Supported FPGA RAMs are:                                    ////
+////  - Generic FPGA (VENDOR_FPGA)                                ////
+////    Tested RAMs: Altera, Xilinx                               ////
+////    Synthesis tools: LeonardoSpectrum, Synplicity             ////
+////  - Xilinx (VENDOR_XILINX)                                    ////
+////  - Altera (VENDOR_ALTERA)                                    ////
+////                                                              ////
+////  To Do:                                                      ////
+////   - fix Avant!                                               ////
+////   - add additional RAMs (VS etc)                             ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Richard Herveille, richard@asics.ws                   ////
+////      - Damjan Lampret, lampret@opencores.org                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.2  2001/11/08 19:11:31  samg
+// added valid checks to behvioral model
+//
+// Revision 1.1.1.1  2001/09/14 09:57:10  rherveille
+// Major cleanup.
+// Files are now compliant to Altera & Xilinx memories.
+// Memories are now compatible, i.e. drop-in replacements.
+// Added synthesizeable generic FPGA description.
+// Created "generic_memories" cvs entry.
+//
+// Revision 1.1.1.2  2001/08/21 13:09:27  damjan
+// *** empty log message ***
+//
+// Revision 1.1  2001/08/20 18:23:20  damjan
+// Initial revision
+//
+// Revision 1.1  2001/08/09 13:39:33  lampret
+// Major clean-up.
+//
+// Revision 1.2  2001/07/30 05:38:02  lampret
+// Adding empty directories required by HDL coding guidelines
+//
+//
+
+//`include "timescale.v"
+
+`define VENDOR_FPGA
+//`define VENDOR_XILINX
+//`define VENDOR_ALTERA
+
+module generic_dpram(
+       // Generic synchronous dual-port RAM interface
+       rclk, rrst, rce, oe, raddr, do,
+       wclk, wrst, wce, we, waddr, di
+);
+
+       //
+       // Default address and data buses width
+       //
+       parameter aw = 5;  // number of bits in address-bus
+       parameter dw = 16; // number of bits in data-bus
+
+       //
+       // Generic synchronous double-port RAM interface
+       //
+       // read port
+       input           rclk;  // read clock, rising edge trigger
+       input           rrst;  // read port reset, active high
+       input           rce;   // read port chip enable, active high
+       input           oe;        // output enable, active high
+       input  [aw-1:0] raddr; // read address
+       output [dw-1:0] do;    // data output
+
+       // write port
+       input          wclk;  // write clock, rising edge trigger
+       input          wrst;  // write port reset, active high
+       input          wce;   // write port chip enable, active high
+       input          we;    // write enable, active high
+       input [aw-1:0] waddr; // write address
+       input [dw-1:0] di;    // data input
+
+       //
+       // Module body
+       //
+
+`ifdef VENDOR_FPGA
+       //
+       // Instantiation synthesizeable FPGA memory
+       //
+       // This code has been tested using LeonardoSpectrum and Synplicity.
+       // The code correctly instantiates Altera EABs and Xilinx BlockRAMs.
+       //
+
+       reg [dw-1 :0] mem [(1<<aw) -1:0]; // instantiate memory
+       reg [dw-1:0] do;                  // data output registers
+
+       // read operation
+
+       /*
+       always@(posedge rclk)
+               if (rce)                      // clock enable instructs Xilinx tools to use SelectRAM (LUTS) instead of BlockRAM
+                       do <= #1 mem[raddr];
+       */
+
+       always@(posedge rclk)
+               do <= #1 mem[raddr];
+
+       // write operation
+       always@(posedge wclk)
+               if (we && wce)
+                       mem[waddr] <= #1 di;
+
+`else
+
+`ifdef VENDOR_XILINX
+       //
+       // Instantiation of FPGA memory:
+       //
+       // Virtex/Spartan2 BlockRAMs
+       //
+       xilinx_ram_dp xilinx_ram(
+               // read port
+               .CLKA(rclk),
+               .RSTA(rrst),
+               .ENA(rce),
+               .ADDRA(raddr),
+               .DIA( {dw{1'b0}} ),
+               .WEA(1'b0),
+               .DOA(do),
+
+               // write port
+               .CLKB(wclk),
+               .RSTB(wrst),
+               .ENB(wce),
+               .ADDRB(waddr),
+               .DIB(di),
+               .WEB(we),
+               .DOB()
+       );
+
+       defparam
+               xilinx_ram.dwidth = dw,
+               xilinx_ram.awidth = aw;
+
+`else
+
+`ifdef VENDOR_ALTERA
+       //
+       // Instantiation of FPGA memory:
+       //
+       // Altera FLEX/APEX EABs
+       //
+       altera_ram_dp altera_ram(
+               // read port
+               .rdclock(rclk),
+               .rdclocken(rce),
+               .rdaddress(raddr),
+               .q(do),
+
+               // write port
+               .wrclock(wclk),
+               .wrclocken(wce),
+               .wren(we),
+               .wraddress(waddr),
+               .data(di)
+       );
+
+       defparam
+               altera_ram.dwidth = dw,
+               altera_ram.awidth = aw;
+
+`else
+
+`ifdef VENDOR_ARTISAN
+
+       //
+       // Instantiation of ASIC memory:
+       //
+       // Artisan Synchronous Double-Port RAM (ra2sh)
+       //
+       art_hsdp #(dw, 1<<aw, aw) artisan_sdp(
+               // read port
+               .qa(do),
+               .clka(rclk),
+               .cena(~rce),
+               .wena(1'b1),
+               .aa(raddr),
+               .da( {dw{1'b0}} ),
+               .oena(~oe),
+
+               // write port
+               .qb(),
+               .clkb(wclk),
+               .cenb(~wce),
+               .wenb(~we),
+               .ab(waddr),
+               .db(di),
+               .oenb(1'b1)
+       );
+
+`else
+
+`ifdef VENDOR_AVANT
+
+       //
+       // Instantiation of ASIC memory:
+       //
+       // Avant! Asynchronous Two-Port RAM
+       //
+       avant_atp avant_atp(
+               .web(~we),
+               .reb(),
+               .oeb(~oe),
+               .rcsb(),
+               .wcsb(),
+               .ra(raddr),
+               .wa(waddr),
+               .di(di),
+               .do(do)
+       );
+
+`else
+
+`ifdef VENDOR_VIRAGE
+
+       //
+       // Instantiation of ASIC memory:
+       //
+       // Virage Synchronous 2-port R/W RAM
+       //
+       virage_stp virage_stp(
+               // read port
+               .CLKA(rclk),
+               .MEA(rce_a),
+               .ADRA(raddr),
+               .DA( {dw{1'b0}} ),
+               .WEA(1'b0),
+               .OEA(oe),
+               .QA(do),
+
+               // write port
+               .CLKB(wclk),
+               .MEB(wce),
+               .ADRB(waddr),
+               .DB(di),
+               .WEB(we),
+               .OEB(1'b1),
+               .QB()
+       );
+
+`else
+
+       //
+       // Generic dual-port synchronous RAM model
+       //
+
+       //
+       // Generic RAM's registers and wires
+       //
+       reg     [dw-1:0]        mem [(1<<aw)-1:0];      // RAM content
+       reg     [dw-1:0]        do_reg;            // RAM data output register
+
+       //
+       // Data output drivers
+       //
+       assign do = (oe & rce) ? do_reg : {dw{1'bz}};
+
+       // read operation
+       always @(posedge rclk)
+               if (rce)
+                       do_reg <= #1 (we && (waddr==raddr)) ? {dw{1'b x}} : mem[raddr];
+
+       // write operation
+       always @(posedge wclk)
+               if (wce && we)
+                       mem[waddr] <= #1 di;
+
+
+       // Task prints range of memory
+       // *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations.
+       task print_ram;
+       input [aw-1:0] start;
+       input [aw-1:0] finish;
+       integer rnum;
+       begin
+               for (rnum=start;rnum<=finish;rnum=rnum+1)
+                       $display("Addr %h = %h",rnum,mem[rnum]);
+       end
+       endtask
+
+`endif // !VENDOR_VIRAGE
+`endif // !VENDOR_AVANT
+`endif // !VENDOR_ARTISAN
+`endif // !VENDOR_ALTERA
+`endif // !VENDOR_XILINX
+`endif // !VENDOR_FPGA
+
+endmodule
+
+//
+// Black-box modules
+//
+
+`ifdef VENDOR_ALTERA
+       module altera_ram_dp(
+               data,
+               wraddress,
+               rdaddress,
+               wren,
+               wrclock,
+               wrclocken,
+               rdclock,
+               rdclocken,
+               q) /* synthesis black_box */;
+
+               parameter awidth = 7;
+               parameter dwidth = 8;
+
+               input [dwidth -1:0] data;
+               input [awidth -1:0] wraddress;
+               input [awidth -1:0] rdaddress;
+               input               wren;
+               input               wrclock;
+               input               wrclocken;
+               input               rdclock;
+               input               rdclocken;
+               output [dwidth -1:0] q;
+
+               // synopsis translate_off
+               // exemplar translate_off
+
+               syn_dpram_rowr #(
+                       "UNUSED",
+                       dwidth,
+                       awidth,
+                       1 << awidth
+               )
+               altera_dpram_model (
+                       // read port
+                       .RdClock(rdclock),
+                       .RdClken(rdclocken),
+                       .RdAddress(rdaddress),
+                       .RdEn(1'b1),
+                       .Q(q),
+
+                       // write port
+                       .WrClock(wrclock),
+                       .WrClken(wrclocken),
+                       .WrAddress(wraddress),
+                       .WrEn(wren),
+                       .Data(data)
+               );
+
+               // exemplar translate_on
+               // synopsis translate_on
+
+       endmodule
+`endif // VENDOR_ALTERA
+
+`ifdef VENDOR_XILINX
+       module xilinx_ram_dp (
+               ADDRA,
+               CLKA,
+               ADDRB,
+               CLKB,
+               DIA,
+               WEA,
+               DIB,
+               WEB,
+               ENA,
+               ENB,
+               RSTA,
+               RSTB,
+               DOA,
+               DOB) /* synthesis black_box */ ;
+
+       parameter awidth = 7;
+       parameter dwidth = 8;
+
+       // port_a
+       input               CLKA;
+       input               RSTA;
+       input               ENA;
+       input [awidth-1:0]  ADDRA;
+       input [dwidth-1:0]  DIA;
+       input               WEA;
+       output [dwidth-1:0] DOA;
+
+       // port_b
+       input               CLKB;
+       input               RSTB;
+       input               ENB;
+       input [awidth-1:0]  ADDRB;
+       input [dwidth-1:0]  DIB;
+       input               WEB;
+       output [dwidth-1:0] DOB;
+
+       // insert simulation model
+
+
+       // synopsys translate_off
+       // exemplar translate_off
+
+       C_MEM_DP_BLOCK_V1_0 #(
+               awidth,
+               awidth,
+               1,
+               1,
+               "0",
+               1 << awidth,
+               1 << awidth,
+               1,
+               1,
+               1,
+               1,
+               1,
+               1,
+               1,
+               1,
+               1,
+               1,
+               1,
+               1,
+               1,
+               "",
+               16,
+               0,
+               0,
+               1,
+               1,
+               1,
+               1,
+               dwidth,
+               dwidth)
+       xilinx_dpram_model (
+               .ADDRA(ADDRA),
+               .CLKA(CLKA),
+               .ADDRB(ADDRB),
+               .CLKB(CLKB),
+               .DIA(DIA),
+               .WEA(WEA),
+               .DIB(DIB),
+               .WEB(WEB),
+               .ENA(ENA),
+               .ENB(ENB),
+               .RSTA(RSTA),
+               .RSTB(RSTB),
+               .DOA(DOA),
+               .DOB(DOB));
+
+               // exemplar translate_on
+               // synopsys translate_on
+
+       endmodule
+`endif // VENDOR_XILINX
diff --git a/generic_fifo_sc_a.v b/generic_fifo_sc_a.v
new file mode 100644 (file)
index 0000000..2ccd068
--- /dev/null
@@ -0,0 +1,335 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  Universal FIFO Single Clock                                ////
+////                                                             ////
+////                                                             ////
+////  Author: Rudolf Usselmann                                   ////
+////          rudi@asics.ws                                      ////
+////                                                             ////
+////                                                             ////
+////  D/L from: http://www.opencores.org/cores/generic_fifos/    ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
+////                         www.asics.ws                        ////
+////                         rudi@asics.ws                       ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: generic_fifo_sc_a.v,v 1.1.1.1 2002-09-25 05:42:06 rudi Exp $
+//
+//  $Date: 2002-09-25 05:42:06 $
+//  $Revision: 1.1.1.1 $
+//  $Author: rudi $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: not supported by cvs2svn $
+//
+//
+//
+//
+//
+//
+//
+//
+//
+//
+
+`timescale 1ns / 100ps
+`include "generic_dpram.v"
+
+/*
+
+Description
+===========
+
+I/Os
+----
+rst    low active, either sync. or async. master reset (see below how to select)
+clr    synchronous clear (just like reset but always synchronous), high active
+re     read enable, synchronous, high active
+we     read enable, synchronous, high active
+din    Data Input
+dout   Data Output
+
+full   Indicates the FIFO is full (combinatorial output)
+full_r same as above, but registered output (see note below)
+empty  Indicates the FIFO is empty
+empty_r        same as above, but registered output (see note below)
+
+full_n         Indicates if the FIFO has space for N entries (combinatorial output)
+full_n_r       same as above, but registered output (see note below)
+empty_n                Indicates the FIFO has at least N entries (combinatorial output)
+empty_n_r      same as above, but registered output (see note below)
+
+level          indicates the FIFO level:
+               2'b00   0-25%    full
+               2'b01   25-50%   full
+               2'b10   50-75%   full
+               2'b11   %75-100% full
+
+combinatorial vs. registered status outputs
+-------------------------------------------
+Both the combinatorial and registered status outputs have exactly the same
+synchronous timing. Meaning they are being asserted immediately at the clock
+edge after the last read or write. The combinatorial outputs however, pass
+through several levels of logic before they are output. The registered status
+outputs are direct outputs of a flip-flop. The reason both are provided, is
+that the registered outputs require quite a bit of additional logic inside
+the FIFO. If you can meet timing of your device with the combinatorial
+outputs, use them ! The FIFO will be smaller. If the status signals are
+in the critical pass, use the registered outputs, they have a much smaller
+output delay (actually only Tcq).
+
+Parameters
+----------
+The FIFO takes 3 parameters:
+dw     Data bus width
+aw     Address bus width (Determines the FIFO size by evaluating 2^aw)
+n      N is a second status threshold constant for full_n and empty_n
+       If you have no need for the second status threshold, do not
+       connect the outputs and the logic should be removed by your
+       synthesis tool.
+
+Synthesis Results
+-----------------
+In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs
+at about 116 MHz (IO insertion disabled). The registered status outputs
+are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be
+available.
+
+
+Misc
+----
+This design assumes you will do appropriate status checking externally.
+
+IMPORTANT ! writing while the FIFO is full or reading while the FIFO is
+empty will place the FIFO in an undefined state.
+
+*/
+
+
+// Selecting Sync. or Async Reset
+// ------------------------------
+// Uncomment one of the two lines below. The first line for
+// synchronous reset, the second for asynchronous reset
+
+`define SC_FIFO_ASYNC_RESET                            // Uncomment for Syncr. reset
+//`define SC_FIFO_ASYNC_RESET  or negedge rst          // Uncomment for Async. reset
+
+
+module generic_fifo_sc_a(clk, rst, clr, din, we, dout, re,
+                       full, empty, full_r, empty_r,
+                       full_n, empty_n, full_n_r, empty_n_r,
+                       level);
+
+parameter dw=8;
+parameter aw=8;
+parameter n=32;
+parameter max_size = 1<<aw;
+
+input                  clk, rst, clr;
+input  [dw-1:0]        din;
+input                  we;
+output [dw-1:0]        dout;
+input                  re;
+output                 full, full_r;
+output                 empty, empty_r;
+output                 full_n, full_n_r;
+output                 empty_n, empty_n_r;
+output [1:0]           level;
+
+////////////////////////////////////////////////////////////////////
+//
+// Local Wires
+//
+
+reg    [aw-1:0]        wp;
+wire   [aw-1:0]        wp_pl1;
+wire   [aw-1:0]        wp_pl2;
+reg    [aw-1:0]        rp;
+wire   [aw-1:0]        rp_pl1;
+reg                    full_r;
+reg                    empty_r;
+reg                    gb;
+reg                    gb2;
+reg    [aw:0]          cnt;
+wire                   full_n, empty_n;
+reg                    full_n_r, empty_n_r;
+
+////////////////////////////////////////////////////////////////////
+//
+// Memory Block
+//
+
+generic_dpram  #(aw,dw) u0(
+       .rclk(          clk             ),
+       .rrst(          !rst            ),
+       .rce(           1'b1            ),
+       .oe(            1'b1            ),
+       .raddr(         rp              ),
+       .do(            dout            ),
+       .wclk(          clk             ),
+       .wrst(          !rst            ),
+       .wce(           1'b1            ),
+       .we(            we              ),
+       .waddr(         wp              ),
+       .di(            din             )
+       );
+
+////////////////////////////////////////////////////////////////////
+//
+// Misc Logic
+//
+
+always @(posedge clk `SC_FIFO_ASYNC_RESET)
+       if(!rst)        wp <= #1 {aw{1'b0}};
+       else
+       if(clr)         wp <= #1 {aw{1'b0}};
+       else
+       if(we)          wp <= #1 wp_pl1;
+
+assign wp_pl1 = wp + { {aw-1{1'b0}}, 1'b1};
+assign wp_pl2 = wp + { {aw-2{1'b0}}, 2'b10};
+
+always @(posedge clk `SC_FIFO_ASYNC_RESET)
+       if(!rst)        rp <= #1 {aw{1'b0}};
+       else
+       if(clr)         rp <= #1 {aw{1'b0}};
+       else
+       if(re)          rp <= #1 rp_pl1;
+
+assign rp_pl1 = rp + { {aw-1{1'b0}}, 1'b1};
+
+////////////////////////////////////////////////////////////////////
+//
+// Combinatorial Full & Empty Flags
+//
+
+assign empty = ((wp == rp) & !gb);
+assign full  = ((wp == rp) &  gb);
+
+// Guard Bit ...
+always @(posedge clk `SC_FIFO_ASYNC_RESET)
+       if(!rst)                        gb <= #1 1'b0;
+       else
+       if(clr)                         gb <= #1 1'b0;
+       else
+       if((wp_pl1 == rp) & we)         gb <= #1 1'b1;
+       else
+       if(re)                          gb <= #1 1'b0;
+
+////////////////////////////////////////////////////////////////////
+//
+// Registered Full & Empty Flags
+//
+
+// Guard Bit ...
+always @(posedge clk `SC_FIFO_ASYNC_RESET)
+       if(!rst)                        gb2 <= #1 1'b0;
+       else
+       if(clr)                         gb2 <= #1 1'b0;
+       else
+       if((wp_pl2 == rp) & we)         gb2 <= #1 1'b1;
+       else
+       if((wp != rp) & re)             gb2 <= #1 1'b0;
+
+always @(posedge clk `SC_FIFO_ASYNC_RESET)
+       if(!rst)                                full_r <= #1 1'b0;
+       else
+       if(clr)                                 full_r <= #1 1'b0;
+       else
+       if(we & ((wp_pl1 == rp) & gb2) & !re)   full_r <= #1 1'b1;
+       else
+       if(re & ((wp_pl1 != rp) | !gb2) & !we)  full_r <= #1 1'b0;
+
+always @(posedge clk `SC_FIFO_ASYNC_RESET)
+       if(!rst)                                empty_r <= #1 1'b1;
+       else
+       if(clr)                                 empty_r <= #1 1'b1;
+       else
+       if(we & ((wp != rp_pl1) | gb2) & !re)   empty_r <= #1 1'b0;
+       else
+       if(re & ((wp == rp_pl1) & !gb2) & !we)  empty_r <= #1 1'b1;
+
+////////////////////////////////////////////////////////////////////
+//
+// Combinatorial Full_n & Empty_n Flags
+//
+
+assign empty_n = cnt < n;
+assign full_n  = !(cnt < (max_size-n+1));
+assign level = {2{cnt[aw]}} | cnt[aw-1:aw-2];
+
+// N entries status
+always @(posedge clk `SC_FIFO_ASYNC_RESET)
+       if(!rst)        cnt <= #1 {aw+1{1'b0}};
+       else
+       if(clr)         cnt <= #1 {aw+1{1'b0}};
+       else
+       if( re & !we)   cnt <= #1 cnt + { {aw{1'b1}}, 1'b1};
+       else
+       if(!re &  we)   cnt <= #1 cnt + { {aw{1'b0}}, 1'b1};
+
+////////////////////////////////////////////////////////////////////
+//
+// Registered Full_n & Empty_n Flags
+//
+
+always @(posedge clk `SC_FIFO_ASYNC_RESET)
+       if(!rst)                                empty_n_r <= #1 1'b1;
+       else
+       if(clr)                                 empty_n_r <= #1 1'b1;
+       else
+       if(we & (cnt >= (n-1) ) & !re)          empty_n_r <= #1 1'b0;
+       else
+       if(re & (cnt <= n ) & !we)              empty_n_r <= #1 1'b1;
+
+always @(posedge clk `SC_FIFO_ASYNC_RESET)
+       if(!rst)                                full_n_r <= #1 1'b0;
+       else
+       if(clr)                                 full_n_r <= #1 1'b0;
+       else
+       if(we & (cnt >= (max_size-n) ) & !re)   full_n_r <= #1 1'b1;
+       else
+       if(re & (cnt <= (max_size-n+1)) & !we)  full_n_r <= #1 1'b0;
+
+////////////////////////////////////////////////////////////////////
+//
+// Sanity Check
+//
+
+// synopsys translate_off
+always @(posedge clk)
+       if(we & full)
+               $display("%m WARNING: Writing while fifo is FULL (%t)",$time);
+
+always @(posedge clk)
+       if(re & empty)
+               $display("%m WARNING: Reading while fifo is EMPTY (%t)",$time);
+// synopsys translate_on
+endmodule
diff --git a/iCEburn.py b/iCEburn.py
new file mode 100755 (executable)
index 0000000..5a75c4d
--- /dev/null
@@ -0,0 +1,75 @@
+#!/usr/bin/python3
+import argparse
+from libiceblink import ICE40Board, M25P10
+
+def main():
+    ap = argparse.ArgumentParser()
+    ap.add_argument("-e", "--erase", action="store_true")
+    ap.add_argument("-v", "--verbose", action="store_true")
+    ap.add_argument("-w", "--write", type=argparse.FileType("rb"))
+    args = ap.parse_args()
+
+    board = ICE40Board()
+
+    if args.verbose:
+        print("Found iCE40 board serial: %s" % board.get_serial())
+
+
+    sp = board.get_spi_port(0)
+
+    with board.get_gpio() as gpio:
+        # Force the FPGA into reset so we may drive the IOs
+        gpio.ice40SetReset(True)
+
+        with board.get_spi_port(0) as sp:
+            sp.setSpeed(50000000)
+            sp.setMode()
+
+            flash = M25P10(sp.io)
+
+            flash.wakeup()
+            
+            # Verify that we're talking to the part we think we are
+            assert flash.getID() == b'\x20\x20\x11'
+
+            # Now, do the actions
+            if args.erase:
+                if args.verbose:
+                    print("Erasing flash...")
+                flash.chipErase()
+                if args.verbose:
+                    print("")
+
+            if args.write:
+                data = args.write.read()
+
+                if args.verbose:
+                    print("Writing image...")
+
+                for addr in range(0, len(data), 256):
+                    buf = data[addr:addr+256]
+                    flash.pageProgram(addr, buf)
+
+                if args.verbose:
+                    print("Verifying written image...")
+                # Now verify
+                buf = flash.read(0, len(data))
+                assert len(buf) == len(data)
+            
+                nvfailures = 0
+                for i,(a,b) in enumerate(zip(buf, data)):
+                    if a!=b:
+                        print ("verification failure at %06x: %02x != %02x" %
+                               (i,a,b))
+                        nvfailures += 1
+
+                    if nvfailures == 5:
+                        print("Too many verification failures, bailing")
+                        break
+
+        # Release the FPGA reset
+        gpio.ice40SetReset(False)
+
+
+if __name__ == "__main__":
+    main()
diff --git a/libiceblink.py b/libiceblink.py
new file mode 100644 (file)
index 0000000..6cdfe1e
--- /dev/null
@@ -0,0 +1,376 @@
+import usb.core
+import usb.util
+import array
+import struct
+import binascii
+import time
+
+class ProtocolError(Exception):
+    pass
+
+class SPIProtocolError(Exception):
+    def __init__(self, cmd, rescode):
+        lut = {
+            3: "Resource in use",
+            4: "Resource not opened",
+            12: "Invalid enum"
+        }
+        if rescode in lut:
+            err = lut[rescode]
+        else:
+            err = "error code %d" % rescode
+
+        ProtocolError.__init__(self, "Command %s failed with error: %s" %( cmd,
+                               err))
+
+class M25P10(object):
+    STAT_BUSY = 0x1
+    STAT_WEL = 0x2
+
+    CMD_GET_STATUS = 0x05
+    CMD_WRITE_ENABLE = 0x6
+    CMD_READ_ID = 0x9F
+    CMD_WAKEUP = 0xAB
+    CMD_CHIP_ERASE = 0xC7
+    CMD_PAGE_PROGRAM = 0x02
+    CMD_FAST_READ = 0xB
+
+    def __init__(self, iofn):
+        self.io = iofn
+
+    def wakeup(self):
+        self.io([self.CMD_WAKEUP])
+
+    def setWritable(self):
+        self.io([self.CMD_WRITE_ENABLE])
+
+    def chipErase(self):
+        self.setWritable()
+        self.io([self.CMD_CHIP_ERASE])
+        self.waitDone()
+
+    def read(self, addr, size):
+        return self.io([self.CMD_FAST_READ, (addr>>16) & 0xFF, (addr>>8)&0xFF, addr &
+                        0xFF, 0x00], size+5)[5:]
+    def pageProgram(self, addr, buf):
+        self.setWritable()
+        assert len(buf) <= 256
+        assert addr & 0xFF == 0
+
+        self.io([self.CMD_PAGE_PROGRAM, (addr>>16) & 0xFF, (addr>>8)&0xFF, addr &
+                 0xFF] + list(buf))
+        self.waitDone()
+
+    def waitDone(self):
+        while self.getStatus() & self.STAT_BUSY:
+            pass
+
+    def getStatus(self):
+        return self.io([self.CMD_GET_STATUS],2)[1]
+
+    def getID(self):
+        return self.io([self.CMD_READ_ID],4)[1:]
+
+
+class ICE40Board(object):
+
+    CMD_GET_BOARD_TYPE = 0xE2
+    CMD_GET_BOARD_SERIAL = 0xE4
+
+    class __ICE40BoardComm(object):
+        def __init__(self, dev):
+            self.__is_open = False
+            self.dev = dev
+
+        def __enter__(self):
+            self.open()
+            return self
+        
+        def __exit__(self, type, err, traceback):
+            self.__cleanup()
+
+        def __del__(self):
+            self.__cleanup()
+
+        def __cleanup(self):
+            if self.__is_open:
+                self.close()
+
+        def open(self):
+            assert not self.__is_open
+            self.dev.checked_cmd(0x04, 0x00, "bcommopen", [0x00], noret=True)
+            self.__is_open = True
+
+        def close(self):
+            assert self.__is_open
+            self.dev.checked_cmd(0x04, 0x01, "bcommclose", [0x00], noret=True,
+                                 )
+            self.__is_open = False
+
+        def __check_counts(self, status, resb, wr, rd):
+            if status & 0x80:
+                wb = struct.unpack('<L', resb[:4])[0]
+                resb = resb[4:]
+                #print (wb, write_byte_count)
+                assert wb == wr
+                
+            if status & 0x40:
+                rb = struct.unpack('<L', resb[:4])[0]
+                resb = resb[4:]
+                assert rb == rd
+
+        def readReg(self, regno):
+            self.dev.checked_cmd(0x04, 0x05, "bcommsetval", [0x00, regno, 
+                                                             0x01, 0x00, 0x00, 0x0])
+            res = self.dev.ep_datain.read(1)
+            status, pl = self.dev.cmd(0x04, 0x85, [0x00])
+            self.__check_counts(status, pl, 0, 1)
+            return res[0]
+
+        def writeReg(self, regno, value):
+            self.dev.checked_cmd(0x04, 0x04, "bcommsetval", [0x00, regno,
+                                                             0x01, 0x00, 0x00, 0x0])
+            self.dev.ep_dataout.write([value])
+            status, pl = self.dev.cmd(0x04, 0x85, [0x00])
+            self.__check_counts(status, pl, 1, 0)
+
+        def readMulti(self, addrs):
+            pass
+
+        def writeMulti(self, addrvals):
+            pass
+
+    class __ICE40GPIO(object):
+        def __init__(self, dev):
+            self.__is_open = False
+            self.dev = dev
+
+        def __enter__(self):
+            self.open()
+            return self
+
+        def __exit__(self, type, err, traceback):
+            self.__cleanup()
+
+        def __del__(self):
+            self.__cleanup()
+
+        def open(self):
+            assert not self.__is_open
+            # Some kind of open
+            self.dev.checked_cmd(0x03, 0x00, "gpioopen", [0x00], noret=True)
+            self.__is_open = True
+            
+        def close(self):
+            assert self.__is_open
+            self.dev.checked_cmd(0x03, 0x01, "gpioclose", 0x00)
+            self.__is_open = False
+
+        def __cleanup(self):
+            if self.__is_open:
+                self.close()
+
+        def __set_dir(self, direction):
+            self.dev.checked_cmd(0x03, 0x04, "0304", [0x00, direction, 0x00,
+                                                      0x00, 0x00])
+
+        def __set_value(self, value):
+            self.dev.checked_cmd(0x03, 0x06, "0306", [0x00, value, 0x00, 0x00,
+                                                  0x00],noret=True)
+
+        def ice40SetReset(self, assert_reset):
+            if assert_reset:
+                self.__set_dir(1)
+                self.__set_value(0)
+            else:
+                self.__set_dir(0)
+
+
+    class __ICE40SPIPort(object):
+        def __init__(self, dev, portno):
+            self.dev = dev
+            self.__portno = portno
+            assert portno == 0x00
+            self.__is_open = False
+
+        def __enter__(self):
+            self.open()
+            return self
+
+        def __exit__(self, type, exc, traceback):
+            self.__cleanup()
+
+        def __del__(self):
+            self.__cleanup()
+
+        def __cleanup(self):
+            if self.__is_open:
+                self.close()
+
+        def io(self, write_bytes, read_byte_count=0):
+            assert self.__is_open
+            write_bytes = list(write_bytes)
+
+            # Pad write bytes to include 00's for readback
+            if len(write_bytes) < read_byte_count:
+                write_bytes.extend([0] * (read_byte_count - len(write_bytes)))
+
+            write_byte_count = len(write_bytes)
+            read_bytes = []
+
+            # probably assert nCS
+            self.dev.checked_cmd(0x06, 0x06, "SPIStart", [0x00, 0x00])
+
+
+            # Start IO txn
+            self.dev.checked_cmd(0x06, 0x07, "SPIIOStart", 
+
+                 # the meaning of the first 3 bytes is unknown
+                 struct.pack("<BBBBL", 0x00, 0x00, 0x00, 
+                             0x01 if read_byte_count else 0x00,
+                             write_byte_count),noret=True)
+
+            # Do the IO
+            while write_bytes or len(read_bytes) < read_byte_count:
+                if write_bytes:
+                    self.dev.ep_dataout.write(write_bytes[:64])
+                    write_bytes = write_bytes[64:]
+
+                if read_byte_count:
+                    to_read = min(64, read_byte_count) 
+                    read_bytes.extend(self.dev.ep_datain.read(to_read))
+
+
+
+            # End IO txn
+            status, resb =self.dev.cmd(0x06, 0x87,[0x00])
+           
+            # status & 0x80 indicates presence of write size
+            # status & 0x40 indicates presence of read size
+            # validate values
+            if status & 0x80:
+                wb = struct.unpack('<L', resb[:4])[0]
+                resb = resb[4:]
+                #print (wb, write_byte_count)
+                assert wb == write_byte_count
+                
+            if status & 0x40:
+                rb = struct.unpack('<L', resb[:4])[0]
+                resb = resb[4:]
+                assert rb == read_byte_count
+
+            # Clear CS
+            self.dev.checked_cmd(0x06, 0x06, "0606", [0x00, 0x01])
+
+            return bytes(read_bytes)
+
+        def open(self):
+            assert not self.__is_open
+            pl = self.dev.checked_cmd(0x06, 0x00, "SPIOpen", [self.__portno])
+            assert len(pl) == 0
+            self.__is_open = True
+
+        def close(self):
+            pl = self.dev.checked_cmd(0x06, 0x01, "SPIClose", [self.__portno])
+            assert len(pl) == 0
+            self.__is_open = False
+
+        def setMode(self):
+            """May be mode-setting. [0,2] causes bits to be returned shifted right
+            one"""
+            assert self.__is_open
+            pl = self.dev.checked_cmd(0x06, 0x05, "SpiMode", [0,0])
+            assert len(pl) == 0
+
+        def setSpeed(self, speed):
+            """ sets the desired speed for the SPI interface. Returns actual speed
+            set"""
+            pl = self.dev.checked_cmd(0x06, 0x03, "SPISpeed", b'\x00' +
+                                  struct.pack("<L", speed))
+            assert self.__is_open
+            return (struct.unpack("<L",pl),)
+
+
+    def __init__(self):
+        # find our self.device
+        self.dev = usb.core.find(idVendor=0x1443, idProduct=0x0007)
+        if self.dev is None:
+            raise ValueError('Device not found')
+
+        self.dev.set_configuration()
+        
+        # get an endpoint instance
+        cfg = self.dev.get_active_configuration()
+        intf = usb.util.find_descriptor(cfg)
+
+        # Allocate and verify all the endpoints used for comms
+        self.ep_cmdout  = usb.util.find_descriptor(intf, bEndpointAddress = 1)
+        self.ep_cmdin   = usb.util.find_descriptor(intf, bEndpointAddress = 0x82)
+        self.ep_dataout = usb.util.find_descriptor(intf, bEndpointAddress = 3)
+        self.ep_datain  = usb.util.find_descriptor(intf, bEndpointAddress = 0x84)
+
+        assert self.ep_cmdout is not None
+        assert self.ep_cmdin is not None
+        assert self.ep_dataout is not None
+        assert self.ep_datain is not None
+
+        # Make sure we're talking to what we expect
+        btype = self.get_board_type()
+        assert btype == 'iCE40'
+
+    def get_spi_port(self, pn):
+        return self.__ICE40SPIPort(self, pn)
+
+    def get_gpio(self):
+        return self.__ICE40GPIO(self)
+
+    def get_board_comm(self):
+        return self.__ICE40BoardComm(self)
+
+    def ctrl(self, selector, size_or_data, show=False):
+        val = self.dev.ctrl_transfer(0xC0 if isinstance(size_or_data, int) else 0x04, 
+                          selector, 0x00, 0x00, size_or_data)
+        if show and isinstance(val, array.array):
+            print("%2x < %s" % (selector, "".join("%02x" % i for i in val)))
+        return bytes(val)
+
+    def checked_cmd(self, cmd, subcmd, name, payload=[], ressize=16, show=False,
+                   noret=False):
+        status, respl = self.cmd(cmd, subcmd, payload, ressize, show)
+        if status != 0:
+            raise SPIProtocolError(name, status)
+        if noret:
+            assert len(respl) == 0
+        return respl
+
+    def cmd(self, cmd, subcmd, payload, ressize=16, show=False):
+        res = self.cmd_i(
+            struct.pack("<BB", cmd, subcmd) + bytes(payload),
+            ressize)
+
+        status = res[0]
+        if show:
+            print ("%02x:%02x (%s) < %02x:(%s)" % (cmd, subcmd,
+                                              binascii.hexlify(bytes(payload)).decode('ascii'),
+                                              status,
+                                                   binascii.hexlify(res[1:]).decode('ascii')))
+        return status, res[1:]
+
+    def cmd_i(self, cmd_bytes, result_size, show=False):
+        payload = struct.pack('<B', len(cmd_bytes)) + bytes(cmd_bytes)
+        self.ep_cmdout.write(payload)
+        res = bytes(self.ep_cmdin.read(result_size))
+
+        if show:
+            print("%s:%s" % (binascii.hexlify(payload).decode('ascii'),
+                             binascii.hexlify(res).decode('ascii')))
+        assert res[0] == len(res[1:])
+        return res[1:]
+
+    def get_board_type(self):
+        btype = self.ctrl(0xE2, 16)
+        return btype[:btype.index(b'\x00')].decode('ascii')
+
+    def get_serial(self):
+        return self.ctrl(0xE4, 16).decode('ascii')
+
diff --git a/multiple_trigger.v b/multiple_trigger.v
new file mode 100644 (file)
index 0000000..01a8faf
--- /dev/null
@@ -0,0 +1,20 @@
+// Take variable duration pulse which may be high at any time and generate multiple cycle
+// high pulses alligned with the positive edge of the clock pulse.
+
+module MULTIPLE_TRIGGER  #(parameter BITS = 4) (input clk, input trigger_in, output[BITS-1:0] trigger_out);
+
+   reg [BITS-1:0] trigger = 0;
+
+   reg last_trigger_in = 0;
+   
+   always @ (posedge clk) begin
+
+      trigger <= { trigger[BITS-2:0], (!last_trigger_in & trigger_in) };
+
+      last_trigger_in <= trigger_in;
+      
+   end
+
+   assign trigger_out = trigger;
+   
+endmodule
diff --git a/prescaler.v b/prescaler.v
new file mode 100644 (file)
index 0000000..368a94f
--- /dev/null
@@ -0,0 +1,15 @@
+// Prescalar with default 16 bit division
+
+module PRESCALER #(parameter BITS = 16) (input clk, output out);
+   
+    reg [BITS-1:0] counter = 0;
+    always @ (posedge clk) begin      
+    
+        counter <= counter + 1;
+    
+    end
+
+   assign out = counter[BITS-1];
+   
+endmodule
diff --git a/processor_32.v b/processor_32.v
new file mode 100644 (file)
index 0000000..72b158f
--- /dev/null
@@ -0,0 +1,219 @@
+`include "ram.v"
+`include "prescaler.v"
+`include "single_trigger.v"
+`include "multiple_trigger.v"
+
+`define INST_JMP           3'b000
+`define INST_JPR           3'b001
+`define INST_LDN           3'b010
+`define INST_STO           3'b011
+`define INST_SUB           3'b100
+`define INST_SKN           3'b110
+`define INST_HALT          3'b111
+
+`define PC_INC_BUTTON      buttons[8]
+`define PC_DEC_BUTTON      buttons[9]
+`define PAGE_INC_BUTTON    buttons[10]
+`define PAGE_DEC_BUTTON    buttons[11]
+`define PC_CLR_BUTTON      buttons[12]
+`define ACCUM_CLR_BUTTON   buttons[13]
+`define RUN_BUTTON         buttons[14]
+`define EXECUTE_BUTTON     buttons[15] 
+
+function [7:0] reverse (input [7:0] forward);
+   integer i;
+   for (i = 0; i < 8; i = i + 1)
+     reverse[7-i] = forward[i];
+endfunction
+
+function [7:0] select (input condition, input [7:0] word);
+   integer i;
+   select = condition ? word : 8'b00000000;
+endfunction
+  
+// This is a thirty-two bit accumulator machine identical to the Manchester SSEM.
+
+module PROCESSOR (input clk, output [23:0] led, output [3:0] indicators, input [15:0] buttons);
+
+    // We use two clocks - the main one for all the registers and one for the RAM
+    // The RAM clock is twice as fast as the register one to simulate the effect
+    // of flow through RAM which is not supported on the FPGA
+
+    wire clock;
+
+    PRESCALER #(.BITS(2)) scal0 (.clk(clk), .out(clock));
+    
+    // Handle running
+      
+    reg running = 0;
+
+    always @ (posedge `RUN_BUTTON) begin
+    
+        running <= !running;
+    
+    end
+
+    // Generate running clock
+
+    wire running_counter;
+   
+    PRESCALER #(.BITS(6)) scal1 (.clk(clock), .out(running_counter));
+   
+    wire running_clk = running & running_counter;
+   
+    // Handle execution
+
+    wire [4:0] execute_trigger;
+   
+    MULTIPLE_TRIGGER #(.BITS(4)) trig0 (.clk(clock), .trigger_in(!running & `EXECUTE_BUTTON), .trigger_out(execute_trigger));
+
+    wire [4:0] running_trigger;
+
+    MULTIPLE_TRIGGER #(.BITS(5)) trig1 (.clk(clock), .trigger_in(running_clk), .trigger_out(running_trigger));
+
+    wire [4:0] execute = execute_trigger | running_trigger;
+
+    // Handle halt
+
+    reg halt = 0;
+
+    wire newHalt = execute[3] & (inst == `INST_HALT) ? 1 : 
+                        !running ? 0 : 
+                        halt;
+
+    always @ (posedge clock) begin
+
+       halt <= newHalt;
+    
+    end
+   
+    // Handle program space
+
+    // Note that this uses the RAM clock even for the buffer update. Failing to do results in two buffer updates
+    // which leaves the RAM contents unchanged.
+   
+    wire [31:0] pOut;
+
+    wire [7:0] reverseButtons = reverse(buttons[7:0]);
+  
+    wire [31:0] buffer = { select(page == 2'b11, reverseButtons), select(page == 2'b10, reverseButtons), select(page == 2'b01, reverseButtons), select(page == 2'b00, reverseButtons) } ^ pOut;
+    wire write_trigger;
+   
+    wire program_buttons = (buttons[0] | buttons[1] | buttons[2] | buttons[3] | buttons[4] | buttons[5] | buttons[6] | buttons[7]);
+   
+    SINGLE_TRIGGER trig2 (.clk(clk), .trigger_in(program_buttons), .trigger_out(write_trigger));
+
+    wire [4:0] address = (execute[2] | execute[3]) ? addr : pc;
+
+    wire [31:0] pIn = execute[2] & (inst == `INST_STO) ? accum : buffer;
+
+    wire write_enable = (!running & write_trigger) | (execute[2] & (inst == `INST_STO));
+            
+    RAM #(.DATA_BITS(32),.ADDRESS_BITS(5)) programMemory (.clk(clk), .write(write_enable), .addr(address), .in_data(pIn), .out_data(pOut));
+               
+    // Handle page
+   
+    reg [1:0] page = 0;
+
+    wire page_prev_trigger;
+    wire page_next_trigger;
+   
+    SINGLE_TRIGGER trig7 (.clk(clock), .trigger_in(`PAGE_DEC_BUTTON), .trigger_out(page_prev_trigger));
+    SINGLE_TRIGGER trig8 (.clk(clock), .trigger_in(`PAGE_INC_BUTTON), .trigger_out(page_next_trigger));
+
+    wire [1:0] newPage = page_prev_trigger ? (page + 2'b11) : page_next_trigger ? (page + 2'b01) : page;
+
+    always @ (posedge clock) begin
+
+       page <= newPage;
+
+    end
+   
+    // Handle PC
+
+    reg [4:0] pc = 0;
+   
+    wire [4:0] nextPc = pc + 5'b00001;
+    wire [4:0] prevPc = pc + 5'b11111;
+
+    wire pc_prev_trigger;
+    wire pc_next_trigger;
+    wire pc_zero_trigger;
+   
+    SINGLE_TRIGGER trig3 (.clk(clock), .trigger_in(`PC_INC_BUTTON), .trigger_out(pc_next_trigger));
+    SINGLE_TRIGGER trig4 (.clk(clock), .trigger_in(`PC_DEC_BUTTON), .trigger_out(pc_prev_trigger));
+    SINGLE_TRIGGER trig5 (.clk(clock), .trigger_in(`PC_CLR_BUTTON), .trigger_out(pc_zero_trigger));
+
+    wire [4:0] newPc = execute[3] & (inst == `INST_JMP) ? pOut[4:0] :
+                            execute[3] & (inst == `INST_JPR) ? pc + pOut[4:0] :
+                            execute[3] & (inst == `INST_SKN) & (accum[31] == 1) ? nextPc :
+                                  !halt & execute[0] ? nextPc :
+                            !running & pc_zero_trigger ? 5'b00000 : 
+                            !running & pc_next_trigger ? nextPc : 
+                            !running & pc_prev_trigger ? prevPc : 
+                            pc;
+   
+    always @ (posedge clock) begin
+
+       pc <= newPc;
+       
+    end
+
+    // Handle instruction
+                         
+    reg [2:0] inst = 0;
+    reg [4:0] addr = 0;
+
+    wire [2:0] newInst = execute[1] ? pOut[15:13] :
+                         inst;
+
+    wire [4:0] newAddr = execute[1] ? pOut[4:0] :
+                              addr;
+   
+    always @ (posedge clock) begin
+
+       inst <= newInst;
+
+       addr <= newAddr;
+                         
+    end
+                         
+    // Handle accumulator
+
+    reg [31:0] accum = 0;
+
+    wire accum_zero_trigger;
+
+    SINGLE_TRIGGER trig6 (.clk(clock), .trigger_in(`ACCUM_CLR_BUTTON), .trigger_out(accum_zero_trigger));
+
+    wire [31:0] newAccum = execute[2] & (inst == `INST_LDN) ? 0 - pOut :
+                                execute[2] & (inst == `INST_SUB) ? accum - pOut :
+                                      !running & accum_zero_trigger ? 0 :
+                                accum;
+   
+    always @ (posedge clock) begin
+
+      accum <= newAccum;
+       
+    end
+  
+    // Assign the outputs
+
+    wire [7:0] selectedOut = (page == 2'b00) ? pOut[7:0] : 
+                                  (page == 2'b01) ? pOut[15:8] :
+                                (page == 2'b10) ? pOut[23:16] :
+                                  pOut[31:24];
+
+    wire [7:0] selectedAccum = (page == 2'b00) ? accum[7:0] : 
+                                    (page == 2'b01) ? accum[15:8] :
+                                    (page == 2'b10) ? accum[23:16] :
+                                    accum[31:24];
+   
+   assign led[7:0] = reverse(selectedOut);
+   assign led[15:8] = reverse(selectedAccum);
+   assign led[23:16] = {page, 1'b0, pc};
+   assign indicators = {1'b0, (!running & `EXECUTE_BUTTON) | running_clk, halt, running & !halt};
+
+endmodule
+
diff --git a/processor_4.v b/processor_4.v
new file mode 100644 (file)
index 0000000..2184846
--- /dev/null
@@ -0,0 +1,264 @@
+`include "asciihex.v"
+`include "generic_fifo_sc_a.v"
+`include "gc.v"
+`include "ram.v"
+`include "rom.v"
+`include "prescaler.v"
+`include "single_trigger.v"
+`include "uart.v"
+
+`define INST_JPZ           4'b0111
+`define INST_JP            4'b0110
+`define INST_STM           4'b0101
+`define INST_LDM           4'b0100
+`define INST_SUB           4'b0011
+`define INST_ADD           4'b0010
+`define INST_LDI           4'b0001
+`define INST_HALT          4'b0000
+`define INST_READ          4'b1000
+`define INST_WRITE         4'b1001
+`define INST_CONS          4'b1010
+`define INST_LDQ           4'b1110
+`define INST_RDQ           4'b1100
+`define INST_CAR           4'b1111
+`define INST_CDR           4'b1101
+
+`define STORE_BUTTON       buttons[8]
+`define CLEAR_BUTTON       buttons[9]
+`define PC_INC_BUTTON      buttons[10]
+`define PC_DEC_BUTTON      buttons[11]
+`define PC_CLR_BUTTON      buttons[12]
+`define ACCUM_CLR_BUTTON   buttons[13]
+`define RUN_BUTTON         buttons[14]
+`define EXECUTE_BUTTON     buttons[15]
+
+`define GCOP_NOP      4'd0
+`define GCOP_CDR      4'd1
+`define GCOP_CAR      4'd2
+`define GCOP_CDRQ     4'd3
+`define GCOP_CARQ     4'd4
+`define GCOP_CARR     4'd5
+`define GCOP_CDRRX    4'd6
+`define GCOP_CARRX    4'd7
+`define GCOP_CDRQX    4'd8
+`define GCOP_CONS     4'd9
+`define GCOP_XCONS    4'd10
+`define GCOP_RPLACDR  4'd11
+`define GCOP_LDQ      4'd12
+`define GCOP_RDQ      4'd13
+`define GCOP_RDQA     4'd14
+`define GCOP_RDQCDRRX 4'd15
+
+// This is a simple four bit accumulator machine. It is a Havard architecture with separate
+// program and user memory address spaces.
+
+module PROCESSOR (input clk, output [23:0] led, output [3:0] indicators, input [15:0] buttons, output uart_tx, input uart_rx);
+   // storage unit
+   reg  [7:0] Ein;
+   wire [7:0] Eout;
+   reg  [3:0] gcop = 4'b0;
+   wire [6:0] ostate;
+   wire          step_eval;
+
+   reg                   reading_E      = 0;
+
+   // Handle running
+
+   reg running = 1;
+
+   always @ (posedge `RUN_BUTTON) begin
+      running <= !running;
+   end
+
+   // Generate running clock
+
+   wire running_counter;
+
+   PRESCALER #(.BITS(1)) scal0 (.clk(clk), .out(running_counter));
+
+   wire running_clk = running & running_counter;
+
+   // Handle execution
+
+   wire execute_trigger;
+
+   SINGLE_TRIGGER trig0 (.clk(clk), .trigger_in(`EXECUTE_BUTTON), .trigger_out(execute_trigger));
+
+   wire running_trigger;
+
+   SINGLE_TRIGGER trig1 (.clk(clk), .trigger_in(running_clk), .trigger_out(running_trigger));
+
+   wire gc_clock = (!running & execute_trigger) | running_clk;
+   wire eval_clock = !gc_clock & step_eval;
+
+   GC gc (.clk(gc_clock), .mclk(clk), .Ein(Ein), .Eout(Eout), .gcop(gcop), .ostate(ostate), .step_eval(step_eval));
+
+   // Handle halt
+
+   reg  halt = 0;
+
+   always @ (posedge eval_clock) begin
+      if (inst == `INST_HALT)
+        halt <= 1;
+
+      if (!running)
+        halt <= 0;
+   end
+
+   // UART outputs
+   wire       uart_rx_signal;
+   wire [7:0] uart_rx_byte;
+   wire       uart_is_receiving;
+   wire       uart_is_transmitting;
+   wire       uart_rx_error;
+
+   // Handle program space
+   wire [7:0] programOut;
+
+   wire [3:0] inst = programOut[7:4];
+   wire [3:0] argu = programOut[3:0];
+
+   ROM programMemory (.clk(clk), .addr(pc), .data(programOut));
+
+   // Input logic
+   wire [3:0] fifo_in;
+   wire [3:0] fifo_out;
+   wire          fifo_full;
+   wire          fifo_empty;
+   wire          fifo_re = eval_clock & inst == `INST_READ & !fifo_empty;
+   wire          fifo_we = uart_rx_signal & !fifo_full;
+
+   ascii_to_hex a2h (.ascii({1'b0, uart_rx_byte[6:0]}), .hex(fifo_in));
+
+   generic_fifo_sc_a #(.dw(4), .aw(4)) fifo
+    (.clk(clk),
+     .rst(1'b1),
+     .re(fifo_re),
+     .we(fifo_we),
+     .din(fifo_in),
+     .dout(fifo_out),
+     .full(fifo_full),
+     .empty(fifo_empty));
+
+   // Output logic
+   reg        started_writing = 0;
+
+   always @ (posedge eval_clock) begin
+      if (started_writing)
+        started_writing <= 0;
+      else if (inst == `INST_WRITE & !uart_is_transmitting)
+        started_writing <= 1;
+   end
+
+   // Handle PC
+   reg [3:0]  pc = 0;
+
+   wire [3:0] next = pc + 4'b0001;
+   wire [3:0] prev = pc + 4'b1111;
+
+   wire       pc_prev_trigger;
+   wire       pc_next_trigger;
+   wire       pc_zero_trigger;
+
+   SINGLE_TRIGGER trig3 (.clk(clk), .trigger_in(`PC_INC_BUTTON), .trigger_out(pc_next_trigger));
+   SINGLE_TRIGGER trig4 (.clk(clk), .trigger_in(`PC_DEC_BUTTON), .trigger_out(pc_prev_trigger));
+   SINGLE_TRIGGER trig5 (.clk(clk), .trigger_in(`PC_CLR_BUTTON), .trigger_out(pc_zero_trigger));
+
+   wire [3:0] newPc =
+                         (inst == `INST_JP) ? argu :
+              (inst == `INST_JPZ) & (accum == 4'b0000) ? argu :
+              started_writing ? next :
+              (inst == `INST_WRITE) ? pc :
+                         (inst == `INST_READ) & !fifo_re ? pc :
+                         (inst == `INST_RDQ) & !reading_E ? pc :
+              (inst != `INST_HALT) ? next :
+/*              !running & pc_zero_trigger ? 4'b00000 :
+              !running & pc_next_trigger ? next :
+              !running & pc_prev_trigger ? prev : */
+              pc;
+
+   always @ (posedge eval_clock) begin
+      pc <= newPc;
+   end
+
+   // Handle user memory
+   wire [3:0] userMemoryOut;
+
+   RAM #(.DATA_BITS(4),.ADDRESS_BITS(4)) userMemory (.clk(clk), .write(eval_clock & (inst == `INST_STM)), .addr(argu), .in_data(accum), .out_data(userMemoryOut));
+
+   // Handle accumulator
+   reg [3:0]  accum = 0;
+
+   wire [3:0] newAccum =
+                         (inst == `INST_LDI) ? argu :
+              (inst == `INST_ADD) ? accum + argu :
+              (inst == `INST_SUB) ? accum - argu :
+              (inst == `INST_LDM) ? userMemoryOut :
+                         fifo_re ? fifo_out :
+                         reading_E ? Eout[3:0] :
+              accum;
+
+   always @ (posedge eval_clock) begin
+      accum <= newAccum;
+   end
+
+   // UART logic
+   wire       uart_tx_signal = started_writing;
+   wire [7:0] uart_tx_byte;
+
+   hex_to_ascii h2a (.hex(accum), .ascii(uart_tx_byte));
+
+   // 300-ish baud uart
+   uart #(.CLOCK_DIVIDE(81)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error));
+
+   // GC logic
+   always @ (posedge eval_clock) begin
+         if (reading_E) begin
+                reading_E <= 0;
+                gcop <= `GCOP_NOP;
+         end else begin
+                if(inst == `INST_CONS) begin
+                       Ein       <= {4'b0, accum};
+                       gcop      <= `GCOP_CONS;
+                end else if(inst == `INST_LDQ) begin
+                       Ein       <= {4'b0, accum};
+                       gcop      <= `GCOP_LDQ;
+                end else if(inst == `INST_RDQ) begin
+                       Ein       <= 8'b0;
+                       reading_E <= 1;
+                       gcop      <= `GCOP_RDQ;
+                end else if(inst == `INST_CAR) begin
+                       Ein       <= {4'b0, accum};
+                       gcop      <= `GCOP_CAR;
+                end else if(inst == `INST_CDR) begin
+                       Ein       <= {4'b0, accum};
+                       gcop      <= `GCOP_CDR;
+                end else begin
+                       Ein       <= 8'b0;
+                       gcop      <= `GCOP_NOP;
+                end
+         end
+   end
+
+   // Assign the outputs
+
+/*   assign led[0] = uart_tx;
+   assign led[1] = uart_is_transmitting;
+   assign led[2] = uart_is_receiving;
+   assign led[3] = uart_rx_signal;
+   assign led[4] = uart_rx_error;
+   assign led[5] = fifo_empty;
+   assign led[6] = fifo_full;
+   assign led[7] = fifo_re;*/
+   assign led[7:4] = Ein[3:0];
+   assign led[3:0] = Eout[3:0];
+//   assign led[15:8] = programOut;
+//   assign led[15:8] = uart_rx_byte;
+   assign led[15] = step_eval;
+   assign led[14] = eval_clock;
+   assign led[13:8] = ostate;
+   assign led[19:16] = pc;
+   assign led[23:20] = accum;
+   assign indicators = {1'b0, (!running & `EXECUTE_BUTTON) | running_clk, halt, running & !halt};
+
+endmodule
diff --git a/ram.v b/ram.v
new file mode 100644 (file)
index 0000000..a7e69fd
--- /dev/null
+++ b/ram.v
@@ -0,0 +1,22 @@
+// RAM module with single input addr, input and output ports, a write enable and clock input.
+// Data is clocked out of, and into, the RAM on positive clock edges.
+
+module RAM #(parameter DATA_BITS = 8,  parameter ADDRESS_BITS = 4)
+
+(input clk, input write, input[ADDRESS_BITS-1:0] addr, input[DATA_BITS-1:0] in_data, output[DATA_BITS-1:0] out_data);
+   
+   reg [DATA_BITS-1:0] memorySpace [0:2**ADDRESS_BITS-1];                          
+
+   reg [DATA_BITS-1:0] data_out_reg;
+   
+   always @ (posedge clk) begin
+
+       if (write) memorySpace[addr] <= in_data;
+
+       data_out_reg <= memorySpace[addr];
+       
+    end
+
+   assign out_data = data_out_reg;
+   
+endmodule
diff --git a/rom.v b/rom.v
new file mode 100644 (file)
index 0000000..cd23054
--- /dev/null
+++ b/rom.v
@@ -0,0 +1,28 @@
+// ROM module with single input addr, output port, and clock input.
+// Data is clocked out of the ROM on positive clock edges.
+
+module ROM (input clk, input [3:0] addr, output reg [7:0] data);
+   always @ (posedge clk) begin
+      case(addr)
+               4'd0:    data <= 8'b0001_0110; // LDI 6
+               4'd1:    data <= 8'b0110_1001; // JP 9
+               4'd2:    data <= 8'b0010_0001; // ADD 1
+               4'd3:    data <= 8'b1001_0000; // WRITE
+               4'd4:    data <= 8'b0110_0010; // JP 2
+               4'd5:    data <= 8'b0000_0000;
+               4'd6:    data <= 8'b0001_0001; // LDI 1
+               4'd7:    data <= 8'b1000_0000; // READ
+               4'd8:    data <= 8'b0110_0111; // JP 7
+               4'd9:    data <= 8'b1110_0000; // LDQ
+               4'd10:   data <= 8'b0001_1100; // LDI 12
+               4'd11:   data <= 8'b1010_0000; // CONS
+               4'd12:   data <= 8'b1100_0000; // RDQ
+               4'd13:   data <= 8'b1101_0000; // CDR
+               4'd14:   data <= 8'b1100_0000; // RDQ
+               4'd15:   data <= 8'b0000_0000;
+               default: data <= 8'bxxxx_xxxx;
+         endcase
+   end
+
+   assign out_data = data_out_reg;
+endmodule
diff --git a/single_trigger.v b/single_trigger.v
new file mode 100644 (file)
index 0000000..1cc2258
--- /dev/null
@@ -0,0 +1,23 @@
+// Take variable duration pulse which may be high at any time and generate a single cycle
+// high pulse alligned with the positive edge of the clock pulse.
+
+module SINGLE_TRIGGER (input clk, input trigger_in, output trigger_out);
+
+   reg trigger = 0;
+
+   reg last_trigger_in = 0;
+   
+   always @ (posedge clk) begin
+
+      if (!last_trigger_in & trigger_in)
+         trigger <= 1;
+      else
+         trigger <= 0;
+
+      last_trigger_in <= trigger_in;
+      
+   end
+
+   assign trigger_out = trigger;
+   
+endmodule
diff --git a/to-philippa.zip b/to-philippa.zip
new file mode 100644 (file)
index 0000000..f24b36b
Binary files /dev/null and b/to-philippa.zip differ
diff --git a/uart.v b/uart.v
new file mode 100644 (file)
index 0000000..6db3650
--- /dev/null
+++ b/uart.v
@@ -0,0 +1,213 @@
+`timescale 1ns / 1ps
+// Documented Verilog UART
+// Copyright (C) 2010 Timothy Goddard (tim@goddard.net.nz)
+// Distributed under the MIT licence.
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in
+// all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+// THE SOFTWARE.
+//
+module uart(
+    input clk, // The master clock for this module
+    input rst, // Synchronous reset.
+    input rx, // Incoming serial line
+    output tx, // Outgoing serial line
+    input transmit, // Signal to transmit
+    input [7:0] tx_byte, // Byte to transmit
+    output received, // Indicated that a byte has been received.
+    output [7:0] rx_byte, // Byte received
+    output is_receiving, // Low when receive line is idle.
+    output is_transmitting, // Low when transmit line is idle.
+    output recv_error // Indicates error in receiving packet.
+    );
+
+parameter CLOCK_DIVIDE = 1302; // clock rate (50Mhz) / (baud rate (9600) * 4)
+
+// States for the receiving state machine.
+// These are just constants, not parameters to override.
+parameter RX_IDLE = 0;
+parameter RX_CHECK_START = 1;
+parameter RX_READ_BITS = 2;
+parameter RX_CHECK_STOP = 3;
+parameter RX_DELAY_RESTART = 4;
+parameter RX_ERROR = 5;
+parameter RX_RECEIVED = 6;
+
+// States for the transmitting state machine.
+// Constants - do not override.
+parameter TX_IDLE = 0;
+parameter TX_SENDING = 1;
+parameter TX_DELAY_RESTART = 2;
+
+reg [10:0] rx_clk_divider = CLOCK_DIVIDE;
+reg [10:0] tx_clk_divider = CLOCK_DIVIDE;
+
+reg [2:0] recv_state = RX_IDLE;
+reg [5:0] rx_countdown;
+reg [3:0] rx_bits_remaining;
+reg [7:0] rx_data;
+
+reg tx_out = 1'b1;
+reg [1:0] tx_state = TX_IDLE;
+reg [5:0] tx_countdown;
+reg [3:0] tx_bits_remaining;
+reg [7:0] tx_data;
+
+assign received = recv_state == RX_RECEIVED;
+assign recv_error = recv_state == RX_ERROR;
+assign is_receiving = recv_state != RX_IDLE;
+assign rx_byte = rx_data;
+
+assign tx = tx_out;
+assign is_transmitting = tx_state != TX_IDLE;
+
+always @(posedge clk) begin
+       if (rst) begin
+               recv_state = RX_IDLE;
+               tx_state = TX_IDLE;
+       end
+
+       // The clk_divider counter counts down from
+       // the CLOCK_DIVIDE constant. Whenever it
+       // reaches 0, 1/16 of the bit period has elapsed.
+   // Countdown timers for the receiving and transmitting
+       // state machines are decremented.
+       rx_clk_divider = rx_clk_divider - 1;
+       if (!rx_clk_divider) begin
+               rx_clk_divider = CLOCK_DIVIDE;
+               rx_countdown = rx_countdown - 1;
+       end
+       tx_clk_divider = tx_clk_divider - 1;
+       if (!tx_clk_divider) begin
+               tx_clk_divider = CLOCK_DIVIDE;
+               tx_countdown = tx_countdown - 1;
+       end
+
+       // Receive state machine
+       case (recv_state)
+               RX_IDLE: begin
+                       // A low pulse on the receive line indicates the
+                       // start of data.
+                       if (!rx) begin
+                               // Wait half the period - should resume in the
+                               // middle of this first pulse.
+                               rx_clk_divider = CLOCK_DIVIDE;
+                               rx_countdown = 2;
+                               recv_state = RX_CHECK_START;
+                       end
+               end
+               RX_CHECK_START: begin
+                       if (!rx_countdown) begin
+                               // Check the pulse is still there
+                               if (!rx) begin
+                                       // Pulse still there - good
+                                       // Wait the bit period to resume half-way
+                                       // through the first bit.
+                                       rx_countdown = 4;
+                                       rx_bits_remaining = 8;
+                                       recv_state = RX_READ_BITS;
+                               end else begin
+                                       // Pulse lasted less than half the period -
+                                       // not a valid transmission.
+                                       recv_state = RX_ERROR;
+                               end
+                       end
+               end
+               RX_READ_BITS: begin
+                       if (!rx_countdown) begin
+                               // Should be half-way through a bit pulse here.
+                               // Read this bit in, wait for the next if we
+                               // have more to get.
+                               rx_data = {rx, rx_data[7:1]};
+                               rx_countdown = 4;
+                               rx_bits_remaining = rx_bits_remaining - 1;
+                               recv_state = rx_bits_remaining ? RX_READ_BITS : RX_CHECK_STOP;
+                       end
+               end
+               RX_CHECK_STOP: begin
+                       if (!rx_countdown) begin
+                               // Should resume half-way through the stop bit
+                               // This should be high - if not, reject the
+                               // transmission and signal an error.
+                               recv_state = rx ? RX_RECEIVED : RX_ERROR;
+                       end
+               end
+               RX_DELAY_RESTART: begin
+                       // Waits a set number of cycles before accepting
+                       // another transmission.
+                       recv_state = rx_countdown ? RX_DELAY_RESTART : RX_IDLE;
+               end
+               RX_ERROR: begin
+                       // There was an error receiving.
+                       // Raises the recv_error flag for one clock
+                       // cycle while in this state and then waits
+                       // 2 bit periods before accepting another
+                       // transmission.
+                       rx_countdown = 8;
+                       recv_state = RX_DELAY_RESTART;
+               end
+               RX_RECEIVED: begin
+                       // Successfully received a byte.
+                       // Raises the received flag for one clock
+                       // cycle while in this state.
+                       recv_state = RX_IDLE;
+               end
+       endcase
+
+       // Transmit state machine
+       case (tx_state)
+               TX_IDLE: begin
+                       if (transmit) begin
+                               // If the transmit flag is raised in the idle
+                               // state, start transmitting the current content
+                               // of the tx_byte input.
+                               tx_data = tx_byte;
+                               // Send the initial, low pulse of 1 bit period
+                               // to signal the start, followed by the data
+                               tx_clk_divider = CLOCK_DIVIDE;
+                               tx_countdown = 4;
+                               tx_out = 0;
+                               tx_bits_remaining = 8;
+                               tx_state = TX_SENDING;
+                       end
+               end
+               TX_SENDING: begin
+                       if (!tx_countdown) begin
+                               if (tx_bits_remaining) begin
+                                       tx_bits_remaining = tx_bits_remaining - 1;
+                                       tx_out = tx_data[0];
+                                       tx_data = {1'b0, tx_data[7:1]};
+                                       tx_countdown = 4;
+                                       tx_state = TX_SENDING;
+                               end else begin
+                                       // Set delay to send out 2 stop bits.
+                                       tx_out = 1;
+                                       tx_countdown = 8;
+                                       tx_state = TX_DELAY_RESTART;
+                               end
+                       end
+               end
+               TX_DELAY_RESTART: begin
+                       // Wait until tx_countdown reaches the end before
+                       // we send another transmission. This covers the
+                       // "stop bit" delay.
+                       tx_state = tx_countdown ? TX_DELAY_RESTART : TX_IDLE;
+               end
+       endcase
+end
+
+endmodule
diff --git a/yosys-sim-script b/yosys-sim-script
new file mode 100755 (executable)
index 0000000..eae3049
--- /dev/null
@@ -0,0 +1,3 @@
+read_verilog -sv flash.v
+prep -top top -nordff
+sim -clock CLK -vcd test.vcd -n 200
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