Add diagrams and pictures
[clump.git] / Makefile
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1DEVICE = hx1k
2
46a95fd3 3all: toplevel.bin
a051754e 4
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5toplevel.bin: master.rpt master.bin worker.rpt worker.bin
6 tools/icestorm/icemulti/icemulti -o toplevel.bin -v -p0 worker.bin master.bin
7
8master.blif: master.v
ffba35f8 9 tools/yosys/yosys -p 'synth_ice40 -top master -blif $@' $<
a051754e 10
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11worker.blif: worker.v
12 tools/yosys/yosys -p 'synth_ice40 -top worker -blif $@' $<
13
14%.asc: %.pcf %.blif
2542aba7 15 tools/arachne-pnr/bin/arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^ -P tq144 -s 4
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17%.bin: %.asc
2ed306f8 18 tools/icestorm/icepack/icepack $< $@
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20%.rpt: %.asc
7560fdba 21 tools/icestorm/icetime/icetime -C tools/icestorm/icebox/chipdb-$(subst hx,,$(subst lp,,$(DEVICE))).txt -d $(DEVICE) -mtr $@ $<
a051754e 22
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23prog: toplevel.bin
24 tools/icestorm/iceprog/iceprog $<
25
26progall: toplevel.bin
27 bash progall.sh
28
29progmaster: master.bin
2ed306f8 30 tools/icestorm/iceprog/iceprog $<
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32clean:
46a95fd3 33 rm -f master.blif master.asc worker.blif worker.asc master.bin worker.bin toplevel.bin
a051754e 34
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36sim:
46a95fd3 37 tools/yosys/yosys -p 'read_verilog -sv -DSIM worker.v; prep -top worker -nordff; sim -clock CLKin -vcd test.vcd -n 3000'
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38
39.PHONY: all prog clean sim
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