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2ed306f8 MG |
1 | `include "asciihex.v" |
2 | `include "generic_fifo_sc_a.v" | |
3 | `include "gc.v" | |
4 | `include "eval.v" | |
5 | `include "ram.v" | |
3f6eb730 | 6 | `include "reader.v" |
2ed306f8 MG |
7 | `include "rom.v" |
8 | `include "prescaler.v" | |
9 | `include "single_trigger.v" | |
10 | `include "uart.v" | |
3f6eb730 | 11 | `include "writer.v" |
2ed306f8 MG |
12 | |
13 | `define GCOP_NOP 4'd0 | |
14 | `define GCOP_CDR 4'd1 | |
15 | `define GCOP_CAR 4'd2 | |
16 | `define GCOP_CDRQ 4'd3 | |
17 | `define GCOP_CARQ 4'd4 | |
18 | `define GCOP_CARR 4'd5 | |
19 | `define GCOP_CDRRX 4'd6 | |
20 | `define GCOP_CARRX 4'd7 | |
21 | `define GCOP_CDRQX 4'd8 | |
22 | `define GCOP_CONS 4'd9 | |
23 | `define GCOP_XCONS 4'd10 | |
24 | `define GCOP_RPLACDR 4'd11 | |
25 | `define GCOP_LDQ 4'd12 | |
26 | `define GCOP_RDQ 4'd13 | |
27 | `define GCOP_RDQA 4'd14 | |
28 | `define GCOP_RDQCDRRX 4'd15 | |
29 | ||
3f6eb730 MG |
30 | `ifdef SIM |
31 | `define UART_DIVIDE 1 | |
32 | `else | |
33 | `define UART_DIVIDE 39 | |
34 | `endif | |
35 | ||
2ed306f8 | 36 | module PROCESSOR (input clk, output [4:0] led, output uart_tx, input uart_rx); |
b5efed3a MG |
37 | wire [15:0] result; |
38 | ||
39 | reg [5:0] initial_reset = 30; | |
40 | always @ (posedge clk) | |
41 | if (initial_reset) initial_reset <= initial_reset - 1; | |
2ed306f8 | 42 | |
3f6eb730 | 43 | wire reset = |initial_reset || reader_active || writer_clock_enable; |
2ed306f8 MG |
44 | reg [1:0] counter = 0; |
45 | ||
3f6eb730 MG |
46 | wire gc_clock_enable = counter[0] & counter[1] & !reset; |
47 | wire eval_clock_enable = counter[0] & !counter[1] & step_eval & !reset; | |
2ed306f8 MG |
48 | |
49 | always @ (posedge clk) | |
50 | counter <= counter + 1; | |
51 | ||
b5efed3a MG |
52 | wire [15:0] E1; |
53 | wire [15:0] E2; | |
2ed306f8 MG |
54 | wire [3:0] gcop; |
55 | wire [5:0] gostate; | |
56 | wire [5:0] eostate; | |
57 | wire conn_ea; | |
58 | wire conn_et; | |
59 | ||
60 | wire step_eval; | |
61 | ||
3f6eb730 MG |
62 | wire gc_ram_we; |
63 | wire [12:0] gc_ram_addr; | |
64 | wire [15:0] gc_ram_di; | |
65 | ||
66 | wire reader_ram_we; | |
67 | wire [12:0] reader_ram_addr; | |
68 | wire [15:0] reader_ram_di; | |
69 | ||
70 | wire [12:0] writer_ram_addr; | |
71 | ||
72 | wire reader_active; | |
73 | ||
74 | wire ram_we = reader_active ? reader_ram_we : gc_ram_we; | |
75 | wire [12:0] ram_addr = reader_active ? reader_ram_addr : writer_clock_enable ? writer_ram_addr : gc_ram_addr; | |
76 | wire [15:0] ram_di = reader_active ? reader_ram_di : gc_ram_di; | |
44b73af5 MG |
77 | wire [15:0] ram_do; |
78 | ||
3f6eb730 MG |
79 | reg writer_clock_enable = 0; |
80 | wire writer_finished; | |
81 | reg will_stop_writer = 0; | |
82 | reg writer_started = 0; | |
83 | ||
44b73af5 MG |
84 | GCRAM gcram (.clk(clk), .we(ram_we), .addr(ram_addr), .di(ram_di), .do(ram_do), .result(result)); |
85 | ||
3f6eb730 MG |
86 | GC gc (.clk(clk), .rst(reset), .clk_enable(gc_clock_enable), .Ein(E1), .Eout(E2), .gcop(gcop), .ostate(gostate), .step_eval(step_eval), .conn_ea(conn_ea), .conn_et(conn_et), .ram_we(gc_ram_we), .ram_addr(gc_ram_addr), .ram_di(gc_ram_di), .ram_do(ram_do)); |
87 | ||
88 | EVAL eval (.clk(clk), .rst(reset), .clk_enable(eval_clock_enable), .Ein(E2), .Eout(E1), .gcop(gcop), .ostate(eostate), .conn_ea(conn_ea), .conn_et(conn_et)); | |
2ed306f8 | 89 | |
3f6eb730 MG |
90 | READER reader (.clk(clk), .clk_enable(!initial_reset), .uart_rx_byte(uart_rx_byte), .uart_rx_signal(uart_rx_signal), .uart_is_receiving(uart_is_receiving), .active(reader_active), .ram_we(reader_ram_we), .ram_addr(reader_ram_addr), .ram_di(reader_ram_di)); |
91 | ||
92 | WRITER writer (.clk(clk), .clk_enable(writer_clock_enable), .uart_tx_byte(uart_tx_byte), .uart_tx_signal(uart_tx_signal), .uart_is_transmitting(uart_is_transmitting), .finished(writer_finished), .result(result)); | |
2ed306f8 MG |
93 | |
94 | // UART outputs | |
95 | wire uart_rx_signal; | |
96 | wire [7:0] uart_rx_byte; | |
97 | wire uart_is_receiving; | |
98 | wire uart_is_transmitting; | |
99 | wire uart_rx_error; | |
100 | ||
2ed306f8 | 101 | // UART logic |
3f6eb730 MG |
102 | wire uart_tx_signal; |
103 | wire [7:0] uart_tx_byte; | |
104 | ||
105 | always @ (posedge clk) begin | |
106 | if(writer_finished) | |
107 | will_stop_writer <= 1; | |
108 | if(will_stop_writer) | |
109 | writer_clock_enable <= 0; | |
110 | ||
111 | if(reader_active) begin | |
112 | writer_started <= 0; | |
113 | will_stop_writer <= 0; | |
114 | end else if(eostate == 5'd7 && !writer_started) begin | |
115 | writer_started <= 1; | |
116 | writer_clock_enable <= 1; | |
117 | end | |
118 | end | |
2ed306f8 MG |
119 | |
120 | // 300 baud uart | |
3f6eb730 | 121 | uart #(.CLOCK_DIVIDE(`UART_DIVIDE)) uart (.clk(clk), .rx(uart_rx), .tx(uart_tx), .transmit(uart_tx_signal), .tx_byte(uart_tx_byte), .received(uart_rx_signal), .rx_byte(uart_rx_byte), .is_receiving(uart_is_receiving), .is_transmitting(uart_is_transmitting), .recv_error (uart_rx_error)); |
2ed306f8 MG |
122 | |
123 | // Assign the outputs | |
3f6eb730 | 124 | assign led[0] = eval_clock_enable; |
2ed306f8 MG |
125 | assign led[1] = uart_is_transmitting; |
126 | assign led[2] = uart_is_receiving; | |
3f6eb730 | 127 | assign led[3] = writer_clock_enable; |
2ed306f8 | 128 | endmodule |