[clump.git] / prescaler.v

// Prescalar with default 16 bit division

module PRESCALER #(parameter BITS = 16) (input clk, output out);
    reg [BITS-1:0] counter = 0;

    always @ (posedge clk) begin
        counter <= counter + 1;
    end

   assign out = counter[BITS-1];
endmodule
Commit	Line	Data
a051754e MG	1	// Prescalar with default 16 bit division
	2
	3	module PRESCALER #(parameter BITS = 16) (input clk, output out);
a051754e	4	reg [BITS-1:0] counter = 0;
9e30ab0c MG	5
9e30ab0c MG	6	always @ (posedge clk) begin
a051754e	7	counter <= counter + 1;
a051754e MG	8	end
	9
	10	assign out = counter[BITS-1];
a051754e	11	endmodule