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Add diagrams and pictures
[clump.git]
/
prescaler.v
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// Prescalar with default 16 bit division
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module PRESCALER #(parameter BITS = 16) (input clk, output out);
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reg [BITS-1:0] counter = 0;
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always @ (posedge clk) begin
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counter <= counter + 1;
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end
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assign out = counter[BITS-1];
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endmodule
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